EDN Simulation Results

Thursday August 08 2024 23:02:08 UTC

GitHub Revision: 3707c48f56

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 96859198578252641766218135484681220968075710602306197013001824903089223290045

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.100s 19.086us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.940s 50.084us 5 5 100.00
V1 csr_rw edn_csr_rw 0.980s 28.836us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.280s 260.063us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.200s 66.307us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.610s 31.746us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.980s 28.836us 20 20 100.00
edn_csr_aliasing 1.200s 66.307us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 6.760s 844.495us 300 300 100.00
V2 csrng_commands edn_genbits 6.760s 844.495us 300 300 100.00
V2 genbits edn_genbits 6.760s 844.495us 300 300 100.00
V2 interrupts edn_intr 1.220s 22.967us 50 50 100.00
V2 alerts edn_alert 1.460s 340.714us 200 200 100.00
V2 errs edn_err 1.380s 30.897us 100 100 100.00
V2 disable edn_disable 0.990s 16.260us 50 50 100.00
edn_disable_auto_req_mode 1.460s 50.497us 50 50 100.00
V2 stress_all edn_stress_all 6.770s 333.912us 50 50 100.00
V2 intr_test edn_intr_test 1.120s 30.976us 50 50 100.00
V2 alert_test edn_alert_test 1.390s 44.400us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.190s 117.184us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.190s 117.184us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.940s 50.084us 5 5 100.00
edn_csr_rw 0.980s 28.836us 20 20 100.00
edn_csr_aliasing 1.200s 66.307us 5 5 100.00
edn_same_csr_outstanding 1.510s 421.908us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.940s 50.084us 5 5 100.00
edn_csr_rw 0.980s 28.836us 20 20 100.00
edn_csr_aliasing 1.200s 66.307us 5 5 100.00
edn_same_csr_outstanding 1.510s 421.908us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 9.860s 2.801ms 5 5 100.00
edn_tl_intg_err 4.380s 225.585us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.000s 15.686us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.460s 340.714us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 9.860s 2.801ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 9.860s 2.801ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 9.860s 2.801ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 9.860s 2.801ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.460s 340.714us 200 200 100.00
edn_sec_cm 9.860s 2.801ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.460s 340.714us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 4.380s 225.585us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 54.424m 135.160ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1130 1130 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.78 98.25 93.97 97.02 93.02 96.37 99.77 92.06

Past Results