EDN Simulation Results

Friday August 09 2024 23:02:07 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39866585070056138360117926942905553094756411441088058786676399955088054585836

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.090s 19.095us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.940s 37.900us 5 5 100.00
V1 csr_rw edn_csr_rw 1.040s 15.751us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 3.680s 278.991us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.250s 100.463us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.700s 25.752us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.040s 15.751us 20 20 100.00
edn_csr_aliasing 1.250s 100.463us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.328m 4.596ms 300 300 100.00
V2 csrng_commands edn_genbits 1.328m 4.596ms 300 300 100.00
V2 genbits edn_genbits 1.328m 4.596ms 300 300 100.00
V2 interrupts edn_intr 1.200s 21.886us 50 50 100.00
V2 alerts edn_alert 1.570s 304.347us 200 200 100.00
V2 errs edn_err 1.440s 60.116us 100 100 100.00
V2 disable edn_disable 0.970s 13.278us 50 50 100.00
edn_disable_auto_req_mode 1.370s 41.736us 50 50 100.00
V2 stress_all edn_stress_all 7.320s 398.428us 50 50 100.00
V2 intr_test edn_intr_test 0.980s 26.051us 50 50 100.00
V2 alert_test edn_alert_test 1.130s 29.785us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 5.430s 603.909us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 5.430s 603.909us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.940s 37.900us 5 5 100.00
edn_csr_rw 1.040s 15.751us 20 20 100.00
edn_csr_aliasing 1.250s 100.463us 5 5 100.00
edn_same_csr_outstanding 1.380s 120.145us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.940s 37.900us 5 5 100.00
edn_csr_rw 1.040s 15.751us 20 20 100.00
edn_csr_aliasing 1.250s 100.463us 5 5 100.00
edn_same_csr_outstanding 1.380s 120.145us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 7.260s 430.899us 5 5 100.00
edn_tl_intg_err 3.100s 579.850us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.060s 14.780us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.570s 304.347us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 7.260s 430.899us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 7.260s 430.899us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 7.260s 430.899us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 7.260s 430.899us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.570s 304.347us 200 200 100.00
edn_sec_cm 7.260s 430.899us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.570s 304.347us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 3.100s 579.850us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 37.333m 513.010ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1130 1130 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.52 98.25 93.91 97.02 91.28 96.37 99.77 92.06

Past Results