ENTROPY_SRC Simulation Results

Tuesday May 07 2024 19:02:25 UTC

GitHub Revision: 18c8953cf1

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 23463731882259624708557902606691160899163550314542713462365308032920382521803

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 4.000s 108.439us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 14.000s 31.466us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 4.000s 28.570us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 14.000s 5.664ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 9.000s 156.730us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 9.000s 100.655us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 4.000s 28.570us 20 20 100.00
entropy_src_csr_aliasing 9.000s 156.730us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 4.000s 108.439us 50 50 100.00
entropy_src_rng 4.767m 10.081ms 300 300 100.00
entropy_src_fw_ov 2.283m 5.047ms 295 300 98.33
V2 firmware_mode entropy_src_fw_ov 2.283m 5.047ms 295 300 98.33
V2 rng_mode entropy_src_rng 4.767m 10.081ms 300 300 100.00
V2 rng_max_rate entropy_src_rng_max_rate 8.833m 10.059ms 387 400 96.75
V2 health_checks entropy_src_rng 4.767m 10.081ms 300 300 100.00
V2 conditioning entropy_src_rng 4.767m 10.081ms 300 300 100.00
V2 interrupts entropy_src_rng 4.767m 10.081ms 300 300 100.00
V2 alerts entropy_src_rng 4.767m 10.081ms 300 300 100.00
entropy_src_functional_alerts 5.000s 211.215us 50 50 100.00
V2 stress_all entropy_src_stress_all 11.000s 259.794us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 10.100m 10.013ms 964 1000 96.40
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 23.000s 4.696ms 50 50 100.00
V2 intr_test entropy_src_intr_test 8.000s 17.424us 50 50 100.00
V2 alert_test entropy_src_alert_test 3.000s 23.203us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 11.000s 1.654ms 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 11.000s 1.654ms 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 14.000s 31.466us 5 5 100.00
entropy_src_csr_rw 4.000s 28.570us 20 20 100.00
entropy_src_csr_aliasing 9.000s 156.730us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 75.988us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 14.000s 31.466us 5 5 100.00
entropy_src_csr_rw 4.000s 28.570us 20 20 100.00
entropy_src_csr_aliasing 9.000s 156.730us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 75.988us 20 20 100.00
V2 TOTAL 2236 2290 97.64
V2S tl_intg_err entropy_src_sec_cm 4.000s 293.038us 5 5 100.00
entropy_src_tl_intg_err 10.000s 114.429us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.767m 10.081ms 300 300 100.00
entropy_src_cfg_regwen 3.000s 29.236us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.767m 10.081ms 300 300 100.00
V2S sec_cm_config_redun entropy_src_rng 4.767m 10.081ms 300 300 100.00
V2S sec_cm_intersig_mubi entropy_src_rng 4.767m 10.081ms 300 300 100.00
entropy_src_fw_ov 2.283m 5.047ms 295 300 98.33
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 10.100m 10.013ms 964 1000 96.40
entropy_src_sec_cm 4.000s 293.038us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 10.100m 10.013ms 964 1000 96.40
entropy_src_sec_cm 4.000s 293.038us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.767m 10.081ms 300 300 100.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 10.100m 10.013ms 964 1000 96.40
entropy_src_sec_cm 4.000s 293.038us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 10.100m 10.013ms 964 1000 96.40
entropy_src_sec_cm 4.000s 293.038us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 10.100m 10.013ms 964 1000 96.40
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 5.000s 211.215us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 10.000s 114.429us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.633m 10.035ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
Unmapped tests entropy_src_intr 28.000s 1.348ms 43 50 86.00
TOTAL 2509 2570 97.63

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 11 11 8 72.73
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
86.33 98.17 95.37 98.33 95.84 88.00 96.88 90.46 57.62

Failure Buckets

Past Results