ENTROPY_SRC Simulation Results

Thursday May 09 2024 19:02:32 UTC

GitHub Revision: 9656691e03

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 30170103562476460183108208532025718695603957360441815475011549460912256789439

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 4.000s 76.833us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 4.000s 38.113us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 4.000s 86.686us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 16.000s 3.037ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 9.000s 279.719us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 4.000s 93.416us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 4.000s 86.686us 20 20 100.00
entropy_src_csr_aliasing 9.000s 279.719us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 4.000s 76.833us 50 50 100.00
entropy_src_rng 4.850m 10.054ms 299 300 99.67
entropy_src_fw_ov 2.517m 5.081ms 294 300 98.00
V2 firmware_mode entropy_src_fw_ov 2.517m 5.081ms 294 300 98.00
V2 rng_mode entropy_src_rng 4.850m 10.054ms 299 300 99.67
V2 rng_max_rate entropy_src_rng_max_rate 9.167m 10.092ms 383 400 95.75
V2 health_checks entropy_src_rng 4.850m 10.054ms 299 300 99.67
V2 conditioning entropy_src_rng 4.850m 10.054ms 299 300 99.67
V2 interrupts entropy_src_rng 4.850m 10.054ms 299 300 99.67
V2 alerts entropy_src_rng 4.850m 10.054ms 299 300 99.67
entropy_src_functional_alerts 5.000s 67.466us 50 50 100.00
V2 stress_all entropy_src_stress_all 10.000s 791.005us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 10.117m 10.013ms 966 1000 96.60
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 26.000s 1.309ms 50 50 100.00
V2 intr_test entropy_src_intr_test 8.000s 18.612us 50 50 100.00
V2 alert_test entropy_src_alert_test 4.000s 21.634us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 7.000s 161.450us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 7.000s 161.450us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 4.000s 38.113us 5 5 100.00
entropy_src_csr_rw 4.000s 86.686us 20 20 100.00
entropy_src_csr_aliasing 9.000s 279.719us 5 5 100.00
entropy_src_same_csr_outstanding 9.000s 58.445us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 4.000s 38.113us 5 5 100.00
entropy_src_csr_rw 4.000s 86.686us 20 20 100.00
entropy_src_csr_aliasing 9.000s 279.719us 5 5 100.00
entropy_src_same_csr_outstanding 9.000s 58.445us 20 20 100.00
V2 TOTAL 2232 2290 97.47
V2S tl_intg_err entropy_src_sec_cm 4.000s 92.097us 5 5 100.00
entropy_src_tl_intg_err 14.000s 67.139us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.850m 10.054ms 299 300 99.67
entropy_src_cfg_regwen 4.000s 15.457us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.850m 10.054ms 299 300 99.67
V2S sec_cm_config_redun entropy_src_rng 4.850m 10.054ms 299 300 99.67
V2S sec_cm_intersig_mubi entropy_src_rng 4.850m 10.054ms 299 300 99.67
entropy_src_fw_ov 2.517m 5.081ms 294 300 98.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 10.117m 10.013ms 966 1000 96.60
entropy_src_sec_cm 4.000s 92.097us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 10.117m 10.013ms 966 1000 96.60
entropy_src_sec_cm 4.000s 92.097us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.850m 10.054ms 299 300 99.67
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 10.117m 10.013ms 966 1000 96.60
entropy_src_sec_cm 4.000s 92.097us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 10.117m 10.013ms 966 1000 96.60
entropy_src_sec_cm 4.000s 92.097us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 10.117m 10.013ms 966 1000 96.60
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 5.000s 67.466us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 14.000s 67.139us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.967m 10.036ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
Unmapped tests entropy_src_intr 14.000s 2.052ms 46 50 92.00
TOTAL 2508 2570 97.59

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 11 11 7 63.64
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
86.53 98.17 95.37 98.33 95.84 88.12 96.88 90.46 58.35

Failure Buckets

Past Results