ENTROPY_SRC Simulation Results

Thursday May 30 2024 19:02:59 UTC

GitHub Revision: 8cb25a6867

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 26638040090898561482658723926798947801831709189350919955228328310045202344042

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 4.000s 26.064us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 4.000s 67.864us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 4.000s 113.220us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 15.000s 1.361ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 8.000s 814.223us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 8.000s 54.365us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 4.000s 113.220us 20 20 100.00
entropy_src_csr_aliasing 8.000s 814.223us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 4.000s 26.064us 50 50 100.00
entropy_src_rng 4.617m 10.076ms 300 300 100.00
entropy_src_fw_ov 2.417m 5.024ms 289 300 96.33
V2 firmware_mode entropy_src_fw_ov 2.417m 5.024ms 289 300 96.33
V2 rng_mode entropy_src_rng 4.617m 10.076ms 300 300 100.00
V2 rng_max_rate entropy_src_rng_max_rate 8.700m 10.084ms 382 400 95.50
V2 health_checks entropy_src_rng 4.617m 10.076ms 300 300 100.00
V2 conditioning entropy_src_rng 4.617m 10.076ms 300 300 100.00
V2 interrupts entropy_src_rng 4.617m 10.076ms 300 300 100.00
V2 alerts entropy_src_rng 4.617m 10.076ms 300 300 100.00
entropy_src_functional_alerts 5.000s 951.042us 50 50 100.00
V2 stress_all entropy_src_stress_all 10.000s 330.139us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 9.667m 10.012ms 961 1000 96.10
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 23.000s 2.384ms 50 50 100.00
V2 intr_test entropy_src_intr_test 8.000s 23.528us 50 50 100.00
V2 alert_test entropy_src_alert_test 4.000s 26.347us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 10.000s 317.782us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 10.000s 317.782us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 4.000s 67.864us 5 5 100.00
entropy_src_csr_rw 4.000s 113.220us 20 20 100.00
entropy_src_csr_aliasing 8.000s 814.223us 5 5 100.00
entropy_src_same_csr_outstanding 4.000s 266.517us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 4.000s 67.864us 5 5 100.00
entropy_src_csr_rw 4.000s 113.220us 20 20 100.00
entropy_src_csr_aliasing 8.000s 814.223us 5 5 100.00
entropy_src_same_csr_outstanding 4.000s 266.517us 20 20 100.00
V2 TOTAL 2222 2290 97.03
V2S tl_intg_err entropy_src_sec_cm 4.000s 63.060us 5 5 100.00
entropy_src_tl_intg_err 10.000s 308.017us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.617m 10.076ms 300 300 100.00
entropy_src_cfg_regwen 4.000s 41.201us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.617m 10.076ms 300 300 100.00
V2S sec_cm_config_redun entropy_src_rng 4.617m 10.076ms 300 300 100.00
V2S sec_cm_intersig_mubi entropy_src_rng 4.617m 10.076ms 300 300 100.00
entropy_src_fw_ov 2.417m 5.024ms 289 300 96.33
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 9.667m 10.012ms 961 1000 96.10
entropy_src_sec_cm 4.000s 63.060us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 9.667m 10.012ms 961 1000 96.10
entropy_src_sec_cm 4.000s 63.060us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.617m 10.076ms 300 300 100.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 9.667m 10.012ms 961 1000 96.10
entropy_src_sec_cm 4.000s 63.060us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 9.667m 10.012ms 961 1000 96.10
entropy_src_sec_cm 4.000s 63.060us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 9.667m 10.012ms 961 1000 96.10
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 5.000s 951.042us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 10.000s 308.017us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.850m 10.085ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
Unmapped tests entropy_src_intr 30.000s 1.959ms 44 50 88.00
TOTAL 2496 2570 97.12

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 11 11 8 72.73
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
86.59 98.21 95.47 98.36 95.84 88.15 96.88 90.46 58.52

Failure Buckets

Past Results