ENTROPY_SRC Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: 2cf28c40e5

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 4.000s 39.621us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 3.000s 49.824us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 3.000s 101.219us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 14.000s 1.050ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 8.000s 1.041ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 4.000s 76.199us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 3.000s 101.219us 20 20 100.00
entropy_src_csr_aliasing 8.000s 1.041ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 4.000s 39.621us 50 50 100.00
entropy_src_rng 4.650m 10.028ms 299 300 99.67
entropy_src_fw_ov 2.533m 5.034ms 293 300 97.67
V2 firmware_mode entropy_src_fw_ov 2.533m 5.034ms 293 300 97.67
V2 rng_mode entropy_src_rng 4.650m 10.028ms 299 300 99.67
V2 rng_max_rate entropy_src_rng_max_rate 8.950m 10.106ms 388 400 97.00
V2 health_checks entropy_src_rng 4.650m 10.028ms 299 300 99.67
V2 conditioning entropy_src_rng 4.650m 10.028ms 299 300 99.67
V2 interrupts entropy_src_rng 4.650m 10.028ms 299 300 99.67
V2 alerts entropy_src_rng 4.650m 10.028ms 299 300 99.67
entropy_src_functional_alerts 5.000s 122.204us 50 50 100.00
V2 stress_all entropy_src_stress_all 9.000s 1.274ms 50 50 100.00
V2 functional_errors entropy_src_functional_errors 9.683m 10.012ms 968 1000 96.80
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 25.000s 1.289ms 50 50 100.00
V2 intr_test entropy_src_intr_test 3.000s 16.644us 50 50 100.00
V2 alert_test entropy_src_alert_test 3.000s 18.619us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 6.000s 47.410us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 6.000s 47.410us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 3.000s 49.824us 5 5 100.00
entropy_src_csr_rw 3.000s 101.219us 20 20 100.00
entropy_src_csr_aliasing 8.000s 1.041ms 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 312.066us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 3.000s 49.824us 5 5 100.00
entropy_src_csr_rw 3.000s 101.219us 20 20 100.00
entropy_src_csr_aliasing 8.000s 1.041ms 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 312.066us 20 20 100.00
V2 TOTAL 2238 2290 97.73
V2S tl_intg_err entropy_src_sec_cm 4.000s 88.240us 5 5 100.00
entropy_src_tl_intg_err 7.000s 660.707us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.650m 10.028ms 299 300 99.67
entropy_src_cfg_regwen 4.000s 31.384us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.650m 10.028ms 299 300 99.67
V2S sec_cm_config_redun entropy_src_rng 4.650m 10.028ms 299 300 99.67
V2S sec_cm_intersig_mubi entropy_src_rng 4.650m 10.028ms 299 300 99.67
entropy_src_fw_ov 2.533m 5.034ms 293 300 97.67
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 9.683m 10.012ms 968 1000 96.80
entropy_src_sec_cm 4.000s 88.240us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 9.683m 10.012ms 968 1000 96.80
entropy_src_sec_cm 4.000s 88.240us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.650m 10.028ms 299 300 99.67
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 9.683m 10.012ms 968 1000 96.80
entropy_src_sec_cm 4.000s 88.240us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 9.683m 10.012ms 968 1000 96.80
entropy_src_sec_cm 4.000s 88.240us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 9.683m 10.012ms 968 1000 96.80
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 5.000s 122.204us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 7.000s 660.707us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.683m 10.058ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
Unmapped tests entropy_src_intr 31.000s 521.268us 38 50 76.00
TOTAL 2506 2570 97.51

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 11 11 7 63.64
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
86.43 98.17 95.37 98.33 95.84 88.15 96.88 90.46 57.95

Failure Buckets

Past Results