ENTROPY_SRC Simulation Results

Thursday May 23 2024 19:02:32 UTC

GitHub Revision: 1579f6a912

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 107680075914347604077716278187232582575581754843183664337576824686885697334979

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 4.000s 92.304us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 3.000s 37.396us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 3.000s 36.511us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 14.000s 2.141ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 8.000s 237.277us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 9.000s 71.817us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 3.000s 36.511us 20 20 100.00
entropy_src_csr_aliasing 8.000s 237.277us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 4.000s 92.304us 50 50 100.00
entropy_src_rng 4.483m 10.019ms 298 300 99.33
entropy_src_fw_ov 2.283m 5.029ms 293 300 97.67
V2 firmware_mode entropy_src_fw_ov 2.283m 5.029ms 293 300 97.67
V2 rng_mode entropy_src_rng 4.483m 10.019ms 298 300 99.33
V2 rng_max_rate entropy_src_rng_max_rate 8.750m 10.040ms 381 400 95.25
V2 health_checks entropy_src_rng 4.483m 10.019ms 298 300 99.33
V2 conditioning entropy_src_rng 4.483m 10.019ms 298 300 99.33
V2 interrupts entropy_src_rng 4.483m 10.019ms 298 300 99.33
V2 alerts entropy_src_rng 4.483m 10.019ms 298 300 99.33
entropy_src_functional_alerts 5.000s 89.591us 50 50 100.00
V2 stress_all entropy_src_stress_all 10.000s 2.066ms 50 50 100.00
V2 functional_errors entropy_src_functional_errors 9.717m 10.013ms 973 1000 97.30
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 23.000s 338.522us 50 50 100.00
V2 intr_test entropy_src_intr_test 3.000s 24.429us 50 50 100.00
V2 alert_test entropy_src_alert_test 4.000s 74.186us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 8.000s 369.113us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 8.000s 369.113us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 3.000s 37.396us 5 5 100.00
entropy_src_csr_rw 3.000s 36.511us 20 20 100.00
entropy_src_csr_aliasing 8.000s 237.277us 5 5 100.00
entropy_src_same_csr_outstanding 10.000s 133.850us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 3.000s 37.396us 5 5 100.00
entropy_src_csr_rw 3.000s 36.511us 20 20 100.00
entropy_src_csr_aliasing 8.000s 237.277us 5 5 100.00
entropy_src_same_csr_outstanding 10.000s 133.850us 20 20 100.00
V2 TOTAL 2235 2290 97.60
V2S tl_intg_err entropy_src_sec_cm 4.000s 835.524us 5 5 100.00
entropy_src_tl_intg_err 11.000s 174.133us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.483m 10.019ms 298 300 99.33
entropy_src_cfg_regwen 3.000s 60.079us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.483m 10.019ms 298 300 99.33
V2S sec_cm_config_redun entropy_src_rng 4.483m 10.019ms 298 300 99.33
V2S sec_cm_intersig_mubi entropy_src_rng 4.483m 10.019ms 298 300 99.33
entropy_src_fw_ov 2.283m 5.029ms 293 300 97.67
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 9.717m 10.013ms 973 1000 97.30
entropy_src_sec_cm 4.000s 835.524us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 9.717m 10.013ms 973 1000 97.30
entropy_src_sec_cm 4.000s 835.524us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.483m 10.019ms 298 300 99.33
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 9.717m 10.013ms 973 1000 97.30
entropy_src_sec_cm 4.000s 835.524us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 9.717m 10.013ms 973 1000 97.30
entropy_src_sec_cm 4.000s 835.524us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 9.717m 10.013ms 973 1000 97.30
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 5.000s 89.591us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 11.000s 174.133us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.583m 10.031ms 49 50 98.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 49 50 98.00
Unmapped tests entropy_src_intr 22.000s 3.773ms 40 50 80.00
TOTAL 2504 2570 97.43

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 11 11 7 63.64
V2S 3 3 3 100.00
V3 2 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
86.11 98.17 95.37 98.33 95.84 87.95 96.88 90.46 56.78

Failure Buckets

Past Results