ENTROPY_SRC Simulation Results

Thursday May 16 2024 19:02:11 UTC

GitHub Revision: 349bab6601

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 60729333463373082946889975499553948547086354767408862399987151421185145065082

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 14.000s 70.273us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 8.000s 97.204us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 8.000s 49.003us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 16.000s 3.641ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 12.000s 76.007us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 4.000s 70.939us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 8.000s 49.003us 20 20 100.00
entropy_src_csr_aliasing 12.000s 76.007us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 14.000s 70.273us 50 50 100.00
entropy_src_rng 4.667m 10.029ms 299 300 99.67
entropy_src_fw_ov 2.417m 5.040ms 293 300 97.67
V2 firmware_mode entropy_src_fw_ov 2.417m 5.040ms 293 300 97.67
V2 rng_mode entropy_src_rng 4.667m 10.029ms 299 300 99.67
V2 rng_max_rate entropy_src_rng_max_rate 8.600m 10.031ms 393 400 98.25
V2 health_checks entropy_src_rng 4.667m 10.029ms 299 300 99.67
V2 conditioning entropy_src_rng 4.667m 10.029ms 299 300 99.67
V2 interrupts entropy_src_rng 4.667m 10.029ms 299 300 99.67
V2 alerts entropy_src_rng 4.667m 10.029ms 299 300 99.67
entropy_src_functional_alerts 14.000s 207.856us 50 50 100.00
V2 stress_all entropy_src_stress_all 16.000s 1.672ms 50 50 100.00
V2 functional_errors entropy_src_functional_errors 9.233m 10.012ms 969 1000 96.90
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 28.000s 683.508us 50 50 100.00
V2 intr_test entropy_src_intr_test 18.000s 18.688us 50 50 100.00
V2 alert_test entropy_src_alert_test 13.000s 70.018us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 14.000s 90.994us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 14.000s 90.994us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 8.000s 97.204us 5 5 100.00
entropy_src_csr_rw 8.000s 49.003us 20 20 100.00
entropy_src_csr_aliasing 12.000s 76.007us 5 5 100.00
entropy_src_same_csr_outstanding 9.000s 31.771us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 8.000s 97.204us 5 5 100.00
entropy_src_csr_rw 8.000s 49.003us 20 20 100.00
entropy_src_csr_aliasing 12.000s 76.007us 5 5 100.00
entropy_src_same_csr_outstanding 9.000s 31.771us 20 20 100.00
V2 TOTAL 2244 2290 97.99
V2S tl_intg_err entropy_src_sec_cm 5.000s 983.057us 5 5 100.00
entropy_src_tl_intg_err 11.000s 193.976us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.667m 10.029ms 299 300 99.67
entropy_src_cfg_regwen 8.000s 102.261us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.667m 10.029ms 299 300 99.67
V2S sec_cm_config_redun entropy_src_rng 4.667m 10.029ms 299 300 99.67
V2S sec_cm_intersig_mubi entropy_src_rng 4.667m 10.029ms 299 300 99.67
entropy_src_fw_ov 2.417m 5.040ms 293 300 97.67
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 9.233m 10.012ms 969 1000 96.90
entropy_src_sec_cm 5.000s 983.057us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 9.233m 10.012ms 969 1000 96.90
entropy_src_sec_cm 5.000s 983.057us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.667m 10.029ms 299 300 99.67
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 9.233m 10.012ms 969 1000 96.90
entropy_src_sec_cm 5.000s 983.057us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 9.233m 10.012ms 969 1000 96.90
entropy_src_sec_cm 5.000s 983.057us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 9.233m 10.012ms 969 1000 96.90
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 14.000s 207.856us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 11.000s 193.976us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.233m 10.026ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
Unmapped tests entropy_src_intr 22.000s 8.057ms 45 50 90.00
TOTAL 2519 2570 98.02

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 11 11 7 63.64
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
86.45 98.19 95.42 98.36 95.88 88.25 97.92 90.46 57.88

Failure Buckets

Past Results