ENTROPY_SRC Simulation Results

Sunday May 19 2024 19:02:23 UTC

GitHub Revision: eb776817a5

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 56458776725427632834749451790671712939002859133119076946547796163671543192855

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 13.000s 182.735us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 8.000s 53.930us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 12.000s 95.270us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 13.000s 528.215us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 9.000s 44.867us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 8.000s 319.948us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 12.000s 95.270us 20 20 100.00
entropy_src_csr_aliasing 9.000s 44.867us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 13.000s 182.735us 50 50 100.00
entropy_src_rng 4.617m 10.030ms 298 300 99.33
entropy_src_fw_ov 2.283m 5.073ms 294 300 98.00
V2 firmware_mode entropy_src_fw_ov 2.283m 5.073ms 294 300 98.00
V2 rng_mode entropy_src_rng 4.617m 10.030ms 298 300 99.33
V2 rng_max_rate entropy_src_rng_max_rate 8.717m 10.053ms 388 400 97.00
V2 health_checks entropy_src_rng 4.617m 10.030ms 298 300 99.33
V2 conditioning entropy_src_rng 4.617m 10.030ms 298 300 99.33
V2 interrupts entropy_src_rng 4.617m 10.030ms 298 300 99.33
V2 alerts entropy_src_rng 4.617m 10.030ms 298 300 99.33
entropy_src_functional_alerts 18.000s 105.095us 50 50 100.00
V2 stress_all entropy_src_stress_all 17.000s 494.697us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 9.917m 10.012ms 977 1000 97.70
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 37.000s 698.529us 50 50 100.00
V2 intr_test entropy_src_intr_test 13.000s 53.796us 50 50 100.00
V2 alert_test entropy_src_alert_test 12.000s 90.211us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 16.000s 116.954us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 16.000s 116.954us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 8.000s 53.930us 5 5 100.00
entropy_src_csr_rw 12.000s 95.270us 20 20 100.00
entropy_src_csr_aliasing 9.000s 44.867us 5 5 100.00
entropy_src_same_csr_outstanding 4.000s 261.758us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 8.000s 53.930us 5 5 100.00
entropy_src_csr_rw 12.000s 95.270us 20 20 100.00
entropy_src_csr_aliasing 9.000s 44.867us 5 5 100.00
entropy_src_same_csr_outstanding 4.000s 261.758us 20 20 100.00
V2 TOTAL 2247 2290 98.12
V2S tl_intg_err entropy_src_sec_cm 4.000s 98.041us 5 5 100.00
entropy_src_tl_intg_err 13.000s 60.095us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.617m 10.030ms 298 300 99.33
entropy_src_cfg_regwen 12.000s 36.933us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.617m 10.030ms 298 300 99.33
V2S sec_cm_config_redun entropy_src_rng 4.617m 10.030ms 298 300 99.33
V2S sec_cm_intersig_mubi entropy_src_rng 4.617m 10.030ms 298 300 99.33
entropy_src_fw_ov 2.283m 5.073ms 294 300 98.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 9.917m 10.012ms 977 1000 97.70
entropy_src_sec_cm 4.000s 98.041us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 9.917m 10.012ms 977 1000 97.70
entropy_src_sec_cm 4.000s 98.041us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.617m 10.030ms 298 300 99.33
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 9.917m 10.012ms 977 1000 97.70
entropy_src_sec_cm 4.000s 98.041us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 9.917m 10.012ms 977 1000 97.70
entropy_src_sec_cm 4.000s 98.041us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 9.917m 10.012ms 977 1000 97.70
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 18.000s 105.095us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 13.000s 60.095us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.333m 10.060ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
Unmapped tests entropy_src_intr 22.000s 3.997ms 40 50 80.00
TOTAL 2517 2570 97.94

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 11 11 7 63.64
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
86.59 98.17 95.37 98.33 95.84 88.05 96.88 90.46 58.66

Failure Buckets

Past Results