ENTROPY_SRC Simulation Results

Sunday June 02 2024 19:02:53 UTC

GitHub Revision: 01a208901a

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 50418669159766293903157726892781832882154091083197082086235277423705989875584

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 4.000s 86.514us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 3.000s 30.080us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 3.000s 31.559us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 14.000s 2.019ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 8.000s 211.714us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 4.000s 29.886us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 3.000s 31.559us 20 20 100.00
entropy_src_csr_aliasing 8.000s 211.714us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 4.000s 86.514us 50 50 100.00
entropy_src_rng 4.850m 10.041ms 300 300 100.00
entropy_src_fw_ov 2.383m 5.027ms 287 300 95.67
V2 firmware_mode entropy_src_fw_ov 2.383m 5.027ms 287 300 95.67
V2 rng_mode entropy_src_rng 4.850m 10.041ms 300 300 100.00
V2 rng_max_rate entropy_src_rng_max_rate 8.867m 10.108ms 384 400 96.00
V2 health_checks entropy_src_rng 4.850m 10.041ms 300 300 100.00
V2 conditioning entropy_src_rng 4.850m 10.041ms 300 300 100.00
V2 interrupts entropy_src_rng 4.850m 10.041ms 300 300 100.00
V2 alerts entropy_src_rng 4.850m 10.041ms 300 300 100.00
entropy_src_functional_alerts 5.000s 372.764us 50 50 100.00
V2 stress_all entropy_src_stress_all 10.000s 2.530ms 50 50 100.00
V2 functional_errors entropy_src_functional_errors 9.483m 10.012ms 965 1000 96.50
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 26.000s 3.953ms 50 50 100.00
V2 intr_test entropy_src_intr_test 4.000s 42.811us 50 50 100.00
V2 alert_test entropy_src_alert_test 4.000s 19.586us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 7.000s 585.883us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 7.000s 585.883us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 3.000s 30.080us 5 5 100.00
entropy_src_csr_rw 3.000s 31.559us 20 20 100.00
entropy_src_csr_aliasing 8.000s 211.714us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 148.366us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 3.000s 30.080us 5 5 100.00
entropy_src_csr_rw 3.000s 31.559us 20 20 100.00
entropy_src_csr_aliasing 8.000s 211.714us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 148.366us 20 20 100.00
V2 TOTAL 2226 2290 97.21
V2S tl_intg_err entropy_src_sec_cm 4.000s 137.359us 5 5 100.00
entropy_src_tl_intg_err 7.000s 175.211us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.850m 10.041ms 300 300 100.00
entropy_src_cfg_regwen 3.000s 50.350us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.850m 10.041ms 300 300 100.00
V2S sec_cm_config_redun entropy_src_rng 4.850m 10.041ms 300 300 100.00
V2S sec_cm_intersig_mubi entropy_src_rng 4.850m 10.041ms 300 300 100.00
entropy_src_fw_ov 2.383m 5.027ms 287 300 95.67
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 9.483m 10.012ms 965 1000 96.50
entropy_src_sec_cm 4.000s 137.359us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 9.483m 10.012ms 965 1000 96.50
entropy_src_sec_cm 4.000s 137.359us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.850m 10.041ms 300 300 100.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 9.483m 10.012ms 965 1000 96.50
entropy_src_sec_cm 4.000s 137.359us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 9.483m 10.012ms 965 1000 96.50
entropy_src_sec_cm 4.000s 137.359us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 9.483m 10.012ms 965 1000 96.50
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 5.000s 372.764us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 7.000s 175.211us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.517m 10.024ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
Unmapped tests entropy_src_intr 23.000s 1.355ms 44 50 88.00
TOTAL 2500 2570 97.28

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 11 11 8 72.73
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
86.57 98.21 95.47 98.36 95.84 87.98 96.88 90.46 58.52

Failure Buckets

Past Results