ENTROPY_SRC Simulation Results

Monday June 24 2024 23:02:35 UTC

GitHub Revision: 6e698b4dfe

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 102849012855470111388983783327793201144267754054590670930996118558901483180117

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 13.000s 150.810us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 4.000s 18.044us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 5.000s 30.720us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 11.000s 158.796us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 8.000s 1.190ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 4.000s 617.929us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 5.000s 30.720us 20 20 100.00
entropy_src_csr_aliasing 8.000s 1.190ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 13.000s 150.810us 50 50 100.00
entropy_src_rng 4.600m 10.016ms 298 300 99.33
entropy_src_fw_ov 2.367m 5.110ms 284 300 94.67
V2 firmware_mode entropy_src_fw_ov 2.367m 5.110ms 284 300 94.67
V2 rng_mode entropy_src_rng 4.600m 10.016ms 298 300 99.33
V2 rng_max_rate entropy_src_rng_max_rate 8.750m 10.068ms 387 400 96.75
V2 health_checks entropy_src_rng 4.600m 10.016ms 298 300 99.33
V2 conditioning entropy_src_rng 4.600m 10.016ms 298 300 99.33
V2 interrupts entropy_src_rng 4.600m 10.016ms 298 300 99.33
V2 alerts entropy_src_rng 4.600m 10.016ms 298 300 99.33
entropy_src_functional_alerts 13.000s 64.854us 50 50 100.00
V2 stress_all entropy_src_stress_all 21.000s 4.213ms 50 50 100.00
V2 functional_errors entropy_src_functional_errors 9.933m 10.013ms 965 1000 96.50
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 27.000s 1.989ms 50 50 100.00
V2 intr_test entropy_src_intr_test 7.000s 27.612us 50 50 100.00
V2 alert_test entropy_src_alert_test 8.000s 99.300us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 8.000s 679.413us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 8.000s 679.413us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 4.000s 18.044us 5 5 100.00
entropy_src_csr_rw 5.000s 30.720us 20 20 100.00
entropy_src_csr_aliasing 8.000s 1.190ms 5 5 100.00
entropy_src_same_csr_outstanding 6.000s 83.219us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 4.000s 18.044us 5 5 100.00
entropy_src_csr_rw 5.000s 30.720us 20 20 100.00
entropy_src_csr_aliasing 8.000s 1.190ms 5 5 100.00
entropy_src_same_csr_outstanding 6.000s 83.219us 20 20 100.00
V2 TOTAL 2224 2290 97.12
V2S tl_intg_err entropy_src_sec_cm 14.000s 112.302us 5 5 100.00
entropy_src_tl_intg_err 9.000s 348.309us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.600m 10.016ms 298 300 99.33
entropy_src_cfg_regwen 18.000s 33.944us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.600m 10.016ms 298 300 99.33
V2S sec_cm_config_redun entropy_src_rng 4.600m 10.016ms 298 300 99.33
V2S sec_cm_intersig_mubi entropy_src_rng 4.600m 10.016ms 298 300 99.33
entropy_src_fw_ov 2.367m 5.110ms 284 300 94.67
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 9.933m 10.013ms 965 1000 96.50
entropy_src_sec_cm 14.000s 112.302us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 9.933m 10.013ms 965 1000 96.50
entropy_src_sec_cm 14.000s 112.302us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.600m 10.016ms 298 300 99.33
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 9.933m 10.013ms 965 1000 96.50
entropy_src_sec_cm 14.000s 112.302us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 9.933m 10.013ms 965 1000 96.50
entropy_src_sec_cm 14.000s 112.302us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 9.933m 10.013ms 965 1000 96.50
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 13.000s 64.854us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 9.000s 348.309us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.500m 10.049ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
Unmapped tests entropy_src_intr 32.000s 4.923ms 44 50 88.00
TOTAL 2498 2570 97.20

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 11 11 7 63.64
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
86.58 98.17 95.37 98.33 95.84 88.15 96.88 90.46 58.56

Failure Buckets

Past Results