ENTROPY_SRC Simulation Results

Tuesday July 02 2024 14:17:13 UTC

GitHub Revision: abd7ce57f2

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 7120396591488306882161367642496372905152431708445539866860566607772054886363

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 13.000s 43.471us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 5.000s 37.472us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 14.000s 38.703us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 14.000s 2.780ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 7.000s 214.007us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 9.000s 52.459us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 14.000s 38.703us 20 20 100.00
entropy_src_csr_aliasing 7.000s 214.007us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 13.000s 43.471us 50 50 100.00
entropy_src_rng 4.683m 10.040ms 298 300 99.33
entropy_src_fw_ov 2.367m 5.058ms 285 300 95.00
V2 firmware_mode entropy_src_fw_ov 2.367m 5.058ms 285 300 95.00
V2 rng_mode entropy_src_rng 4.683m 10.040ms 298 300 99.33
V2 rng_max_rate entropy_src_rng_max_rate 8.617m 10.056ms 384 400 96.00
V2 health_checks entropy_src_rng 4.683m 10.040ms 298 300 99.33
V2 conditioning entropy_src_rng 4.683m 10.040ms 298 300 99.33
V2 interrupts entropy_src_rng 4.683m 10.040ms 298 300 99.33
V2 alerts entropy_src_rng 4.683m 10.040ms 298 300 99.33
entropy_src_functional_alerts 13.000s 121.069us 50 50 100.00
V2 stress_all entropy_src_stress_all 16.000s 135.226us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 10.050m 10.012ms 972 1000 97.20
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 29.000s 334.176us 50 50 100.00
V2 intr_test entropy_src_intr_test 8.000s 69.829us 50 50 100.00
V2 alert_test entropy_src_alert_test 12.000s 35.680us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 8.000s 593.775us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 8.000s 593.775us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 5.000s 37.472us 5 5 100.00
entropy_src_csr_rw 14.000s 38.703us 20 20 100.00
entropy_src_csr_aliasing 7.000s 214.007us 5 5 100.00
entropy_src_same_csr_outstanding 15.000s 155.802us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 5.000s 37.472us 5 5 100.00
entropy_src_csr_rw 14.000s 38.703us 20 20 100.00
entropy_src_csr_aliasing 7.000s 214.007us 5 5 100.00
entropy_src_same_csr_outstanding 15.000s 155.802us 20 20 100.00
V2 TOTAL 2229 2290 97.34
V2S tl_intg_err entropy_src_sec_cm 4.000s 266.491us 5 5 100.00
entropy_src_tl_intg_err 7.000s 187.321us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.683m 10.040ms 298 300 99.33
entropy_src_cfg_regwen 4.000s 23.806us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.683m 10.040ms 298 300 99.33
V2S sec_cm_config_redun entropy_src_rng 4.683m 10.040ms 298 300 99.33
V2S sec_cm_intersig_mubi entropy_src_rng 4.683m 10.040ms 298 300 99.33
entropy_src_fw_ov 2.367m 5.058ms 285 300 95.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 10.050m 10.012ms 972 1000 97.20
entropy_src_sec_cm 4.000s 266.491us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 10.050m 10.012ms 972 1000 97.20
entropy_src_sec_cm 4.000s 266.491us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.683m 10.040ms 298 300 99.33
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 10.050m 10.012ms 972 1000 97.20
entropy_src_sec_cm 4.000s 266.491us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 10.050m 10.012ms 972 1000 97.20
entropy_src_sec_cm 4.000s 266.491us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 10.050m 10.012ms 972 1000 97.20
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 13.000s 121.069us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 7.000s 187.321us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.683m 10.036ms 49 50 98.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 49 50 98.00
Unmapped tests entropy_src_intr 30.000s 498.614us 44 50 88.00
TOTAL 2502 2570 97.35

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 11 11 7 63.64
V2S 3 3 3 100.00
V3 2 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
97.09 98.15 95.32 98.33 95.79 96.62 96.88 90.48 95.54

Failure Buckets

Past Results