ENTROPY_SRC Simulation Results

Saturday June 29 2024 23:02:35 UTC

GitHub Revision: b33f0bcb4a

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 9407974028806500767465982655187958599819354731549473124644158596869486113221

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 13.000s 21.692us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 4.000s 114.357us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 7.000s 14.319us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 15.000s 699.394us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 8.000s 456.450us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 4.000s 36.112us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 7.000s 14.319us 20 20 100.00
entropy_src_csr_aliasing 8.000s 456.450us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 13.000s 21.692us 50 50 100.00
entropy_src_rng 4.600m 10.035ms 297 300 99.00
entropy_src_fw_ov 2.267m 5.018ms 289 300 96.33
V2 firmware_mode entropy_src_fw_ov 2.267m 5.018ms 289 300 96.33
V2 rng_mode entropy_src_rng 4.600m 10.035ms 297 300 99.00
V2 rng_max_rate entropy_src_rng_max_rate 8.750m 10.065ms 382 400 95.50
V2 health_checks entropy_src_rng 4.600m 10.035ms 297 300 99.00
V2 conditioning entropy_src_rng 4.600m 10.035ms 297 300 99.00
V2 interrupts entropy_src_rng 4.600m 10.035ms 297 300 99.00
V2 alerts entropy_src_rng 4.600m 10.035ms 297 300 99.00
entropy_src_functional_alerts 9.000s 94.611us 50 50 100.00
V2 stress_all entropy_src_stress_all 18.000s 1.162ms 50 50 100.00
V2 functional_errors entropy_src_functional_errors 9.233m 10.012ms 968 1000 96.80
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 21.000s 347.719us 50 50 100.00
V2 intr_test entropy_src_intr_test 8.000s 34.175us 50 50 100.00
V2 alert_test entropy_src_alert_test 8.000s 50.483us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 7.000s 223.916us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 7.000s 223.916us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 4.000s 114.357us 5 5 100.00
entropy_src_csr_rw 7.000s 14.319us 20 20 100.00
entropy_src_csr_aliasing 8.000s 456.450us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 76.388us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 4.000s 114.357us 5 5 100.00
entropy_src_csr_rw 7.000s 14.319us 20 20 100.00
entropy_src_csr_aliasing 8.000s 456.450us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 76.388us 20 20 100.00
V2 TOTAL 2226 2290 97.21
V2S tl_intg_err entropy_src_sec_cm 28.000s 55.688us 5 5 100.00
entropy_src_tl_intg_err 7.000s 212.142us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.600m 10.035ms 297 300 99.00
entropy_src_cfg_regwen 13.000s 14.617us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.600m 10.035ms 297 300 99.00
V2S sec_cm_config_redun entropy_src_rng 4.600m 10.035ms 297 300 99.00
V2S sec_cm_intersig_mubi entropy_src_rng 4.600m 10.035ms 297 300 99.00
entropy_src_fw_ov 2.267m 5.018ms 289 300 96.33
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 9.233m 10.012ms 968 1000 96.80
entropy_src_sec_cm 28.000s 55.688us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 9.233m 10.012ms 968 1000 96.80
entropy_src_sec_cm 28.000s 55.688us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.600m 10.035ms 297 300 99.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 9.233m 10.012ms 968 1000 96.80
entropy_src_sec_cm 28.000s 55.688us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 9.233m 10.012ms 968 1000 96.80
entropy_src_sec_cm 28.000s 55.688us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 9.233m 10.012ms 968 1000 96.80
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 9.000s 94.611us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 7.000s 212.142us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.150m 10.087ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
Unmapped tests entropy_src_intr 21.000s 351.255us 44 50 88.00
TOTAL 2500 2570 97.28

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 11 11 7 63.64
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
95.78 98.21 95.48 98.38 95.84 88.35 97.92 90.46 95.66

Failure Buckets

Past Results