ENTROPY_SRC Simulation Results

Friday June 28 2024 23:02:02 UTC

GitHub Revision: 3d5220a43f

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 73442097946972310753089853920865571566707682704390544987111276126114608747389

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 13.000s 25.451us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 8.000s 106.838us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 13.000s 46.091us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 19.000s 2.077ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 8.000s 291.403us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 9.000s 28.339us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 13.000s 46.091us 20 20 100.00
entropy_src_csr_aliasing 8.000s 291.403us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 13.000s 25.451us 50 50 100.00
entropy_src_rng 4.633m 10.078ms 299 300 99.67
entropy_src_fw_ov 2.333m 5.068ms 279 300 93.00
V2 firmware_mode entropy_src_fw_ov 2.333m 5.068ms 279 300 93.00
V2 rng_mode entropy_src_rng 4.633m 10.078ms 299 300 99.67
V2 rng_max_rate entropy_src_rng_max_rate 8.917m 10.066ms 385 400 96.25
V2 health_checks entropy_src_rng 4.633m 10.078ms 299 300 99.67
V2 conditioning entropy_src_rng 4.633m 10.078ms 299 300 99.67
V2 interrupts entropy_src_rng 4.633m 10.078ms 299 300 99.67
V2 alerts entropy_src_rng 4.633m 10.078ms 299 300 99.67
entropy_src_functional_alerts 20.000s 105.568us 50 50 100.00
V2 stress_all entropy_src_stress_all 16.000s 1.517ms 50 50 100.00
V2 functional_errors entropy_src_functional_errors 7.867m 10.012ms 974 1000 97.40
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 30.000s 345.015us 50 50 100.00
V2 intr_test entropy_src_intr_test 8.000s 23.389us 50 50 100.00
V2 alert_test entropy_src_alert_test 14.000s 58.110us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 11.000s 101.706us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 11.000s 101.706us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 8.000s 106.838us 5 5 100.00
entropy_src_csr_rw 13.000s 46.091us 20 20 100.00
entropy_src_csr_aliasing 8.000s 291.403us 5 5 100.00
entropy_src_same_csr_outstanding 9.000s 373.102us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 8.000s 106.838us 5 5 100.00
entropy_src_csr_rw 13.000s 46.091us 20 20 100.00
entropy_src_csr_aliasing 8.000s 291.403us 5 5 100.00
entropy_src_same_csr_outstanding 9.000s 373.102us 20 20 100.00
V2 TOTAL 2227 2290 97.25
V2S tl_intg_err entropy_src_sec_cm 4.000s 88.461us 5 5 100.00
entropy_src_tl_intg_err 11.000s 173.836us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.633m 10.078ms 299 300 99.67
entropy_src_cfg_regwen 15.000s 14.260us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.633m 10.078ms 299 300 99.67
V2S sec_cm_config_redun entropy_src_rng 4.633m 10.078ms 299 300 99.67
V2S sec_cm_intersig_mubi entropy_src_rng 4.633m 10.078ms 299 300 99.67
entropy_src_fw_ov 2.333m 5.068ms 279 300 93.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 7.867m 10.012ms 974 1000 97.40
entropy_src_sec_cm 4.000s 88.461us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 7.867m 10.012ms 974 1000 97.40
entropy_src_sec_cm 4.000s 88.461us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.633m 10.078ms 299 300 99.67
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 7.867m 10.012ms 974 1000 97.40
entropy_src_sec_cm 4.000s 88.461us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 7.867m 10.012ms 974 1000 97.40
entropy_src_sec_cm 4.000s 88.461us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 7.867m 10.012ms 974 1000 97.40
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 20.000s 105.568us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 11.000s 173.836us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.333m 10.081ms 48 50 96.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 48 50 96.00
Unmapped tests entropy_src_intr 20.000s 3.901ms 40 50 80.00
TOTAL 2495 2570 97.08

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 11 11 7 63.64
V2S 3 3 3 100.00
V3 2 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
95.78 98.19 95.43 98.38 95.88 88.37 97.92 90.46 95.66

Failure Buckets

Past Results