ENTROPY_SRC Simulation Results

Thursday June 27 2024 23:02:31 UTC

GitHub Revision: 8db2a18db1

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 100513533386727882033709335126269317053614297947080434367729937568368619502352

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 9.000s 22.431us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 3.000s 28.600us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 4.000s 25.082us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 10.000s 160.557us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 7.000s 210.336us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 4.000s 63.749us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 4.000s 25.082us 20 20 100.00
entropy_src_csr_aliasing 7.000s 210.336us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 9.000s 22.431us 50 50 100.00
entropy_src_rng 4.450m 10.045ms 298 300 99.33
entropy_src_fw_ov 2.283m 5.079ms 290 300 96.67
V2 firmware_mode entropy_src_fw_ov 2.283m 5.079ms 290 300 96.67
V2 rng_mode entropy_src_rng 4.450m 10.045ms 298 300 99.33
V2 rng_max_rate entropy_src_rng_max_rate 8.717m 10.037ms 382 400 95.50
V2 health_checks entropy_src_rng 4.450m 10.045ms 298 300 99.33
V2 conditioning entropy_src_rng 4.450m 10.045ms 298 300 99.33
V2 interrupts entropy_src_rng 4.450m 10.045ms 298 300 99.33
V2 alerts entropy_src_rng 4.450m 10.045ms 298 300 99.33
entropy_src_functional_alerts 13.000s 225.678us 50 50 100.00
V2 stress_all entropy_src_stress_all 18.000s 888.725us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 9.717m 10.012ms 964 1000 96.40
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 25.000s 1.621ms 50 50 100.00
V2 intr_test entropy_src_intr_test 4.000s 16.258us 50 50 100.00
V2 alert_test entropy_src_alert_test 14.000s 19.295us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 8.000s 156.536us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 8.000s 156.536us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 3.000s 28.600us 5 5 100.00
entropy_src_csr_rw 4.000s 25.082us 20 20 100.00
entropy_src_csr_aliasing 7.000s 210.336us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 60.069us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 3.000s 28.600us 5 5 100.00
entropy_src_csr_rw 4.000s 25.082us 20 20 100.00
entropy_src_csr_aliasing 7.000s 210.336us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 60.069us 20 20 100.00
V2 TOTAL 2224 2290 97.12
V2S tl_intg_err entropy_src_sec_cm 5.000s 96.264us 5 5 100.00
entropy_src_tl_intg_err 7.000s 396.726us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.450m 10.045ms 298 300 99.33
entropy_src_cfg_regwen 13.000s 31.327us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.450m 10.045ms 298 300 99.33
V2S sec_cm_config_redun entropy_src_rng 4.450m 10.045ms 298 300 99.33
V2S sec_cm_intersig_mubi entropy_src_rng 4.450m 10.045ms 298 300 99.33
entropy_src_fw_ov 2.283m 5.079ms 290 300 96.67
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 9.717m 10.012ms 964 1000 96.40
entropy_src_sec_cm 5.000s 96.264us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 9.717m 10.012ms 964 1000 96.40
entropy_src_sec_cm 5.000s 96.264us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.450m 10.045ms 298 300 99.33
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 9.717m 10.012ms 964 1000 96.40
entropy_src_sec_cm 5.000s 96.264us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 9.717m 10.012ms 964 1000 96.40
entropy_src_sec_cm 5.000s 96.264us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 9.717m 10.012ms 964 1000 96.40
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 13.000s 225.678us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 7.000s 396.726us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.683m 10.045ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
Unmapped tests entropy_src_intr 28.000s 1.011ms 46 50 92.00
TOTAL 2500 2570 97.28

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 11 11 7 63.64
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
86.55 98.15 95.32 98.33 95.79 88.12 96.88 90.46 58.42

Failure Buckets

Past Results