ENTROPY_SRC Simulation Results

Sunday June 30 2024 23:02:20 UTC

GitHub Revision: b33f0bcb4a

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 105302396297609026156504164956156290718642058150905320202190590799028860124396

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 10.000s 30.253us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 7.000s 83.754us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 4.000s 198.227us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 16.000s 812.582us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 7.000s 426.108us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 6.000s 25.100us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 4.000s 198.227us 20 20 100.00
entropy_src_csr_aliasing 7.000s 426.108us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 10.000s 30.253us 50 50 100.00
entropy_src_rng 4.467m 10.025ms 299 300 99.67
entropy_src_fw_ov 2.400m 5.098ms 281 300 93.67
V2 firmware_mode entropy_src_fw_ov 2.400m 5.098ms 281 300 93.67
V2 rng_mode entropy_src_rng 4.467m 10.025ms 299 300 99.67
V2 rng_max_rate entropy_src_rng_max_rate 8.733m 10.042ms 388 400 97.00
V2 health_checks entropy_src_rng 4.467m 10.025ms 299 300 99.67
V2 conditioning entropy_src_rng 4.467m 10.025ms 299 300 99.67
V2 interrupts entropy_src_rng 4.467m 10.025ms 299 300 99.67
V2 alerts entropy_src_rng 4.467m 10.025ms 299 300 99.67
entropy_src_functional_alerts 14.000s 129.844us 50 50 100.00
V2 stress_all entropy_src_stress_all 18.000s 504.774us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 9.033m 10.012ms 953 1000 95.30
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 32.000s 354.965us 50 50 100.00
V2 intr_test entropy_src_intr_test 4.000s 14.352us 50 50 100.00
V2 alert_test entropy_src_alert_test 18.000s 16.788us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 7.000s 161.965us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 7.000s 161.965us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 7.000s 83.754us 5 5 100.00
entropy_src_csr_rw 4.000s 198.227us 20 20 100.00
entropy_src_csr_aliasing 7.000s 426.108us 5 5 100.00
entropy_src_same_csr_outstanding 7.000s 60.037us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 7.000s 83.754us 5 5 100.00
entropy_src_csr_rw 4.000s 198.227us 20 20 100.00
entropy_src_csr_aliasing 7.000s 426.108us 5 5 100.00
entropy_src_same_csr_outstanding 7.000s 60.037us 20 20 100.00
V2 TOTAL 2211 2290 96.55
V2S tl_intg_err entropy_src_sec_cm 13.000s 139.046us 5 5 100.00
entropy_src_tl_intg_err 11.000s 290.065us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.467m 10.025ms 299 300 99.67
entropy_src_cfg_regwen 14.000s 58.273us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.467m 10.025ms 299 300 99.67
V2S sec_cm_config_redun entropy_src_rng 4.467m 10.025ms 299 300 99.67
V2S sec_cm_intersig_mubi entropy_src_rng 4.467m 10.025ms 299 300 99.67
entropy_src_fw_ov 2.400m 5.098ms 281 300 93.67
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 9.033m 10.012ms 953 1000 95.30
entropy_src_sec_cm 13.000s 139.046us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 9.033m 10.012ms 953 1000 95.30
entropy_src_sec_cm 13.000s 139.046us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.467m 10.025ms 299 300 99.67
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 9.033m 10.012ms 953 1000 95.30
entropy_src_sec_cm 13.000s 139.046us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 9.033m 10.012ms 953 1000 95.30
entropy_src_sec_cm 13.000s 139.046us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 9.033m 10.012ms 953 1000 95.30
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 14.000s 129.844us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 11.000s 290.065us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.317m 10.021ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
Unmapped tests entropy_src_intr 28.000s 995.017us 46 50 92.00
TOTAL 2487 2570 96.77

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 11 11 7 63.64
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
95.79 98.15 95.32 98.36 95.88 88.44 97.92 90.46 95.85

Failure Buckets

Past Results