ENTROPY_SRC Simulation Results

Wednesday July 03 2024 23:02:32 UTC

GitHub Revision: e6706fcc7b

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 8083624550445280117614176890238357255195852125596561370221115831648066795492

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 4.000s 24.278us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 4.000s 88.390us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 4.000s 56.206us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 10.000s 606.468us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 9.000s 483.230us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 4.000s 216.690us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 4.000s 56.206us 20 20 100.00
entropy_src_csr_aliasing 9.000s 483.230us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 4.000s 24.278us 50 50 100.00
entropy_src_rng 4.650m 10.087ms 298 300 99.33
entropy_src_fw_ov 2.350m 5.063ms 292 300 97.33
V2 firmware_mode entropy_src_fw_ov 2.350m 5.063ms 292 300 97.33
V2 rng_mode entropy_src_rng 4.650m 10.087ms 298 300 99.33
V2 rng_max_rate entropy_src_rng_max_rate 8.600m 10.028ms 385 400 96.25
V2 health_checks entropy_src_rng 4.650m 10.087ms 298 300 99.33
V2 conditioning entropy_src_rng 4.650m 10.087ms 298 300 99.33
V2 interrupts entropy_src_rng 4.650m 10.087ms 298 300 99.33
V2 alerts entropy_src_rng 4.650m 10.087ms 298 300 99.33
entropy_src_functional_alerts 4.000s 81.967us 50 50 100.00
V2 stress_all entropy_src_stress_all 9.000s 343.020us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 9.733m 10.013ms 971 1000 97.10
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 23.000s 576.518us 50 50 100.00
V2 intr_test entropy_src_intr_test 4.000s 41.234us 50 50 100.00
V2 alert_test entropy_src_alert_test 3.000s 23.472us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 6.000s 81.351us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 6.000s 81.351us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 4.000s 88.390us 5 5 100.00
entropy_src_csr_rw 4.000s 56.206us 20 20 100.00
entropy_src_csr_aliasing 9.000s 483.230us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 220.597us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 4.000s 88.390us 5 5 100.00
entropy_src_csr_rw 4.000s 56.206us 20 20 100.00
entropy_src_csr_aliasing 9.000s 483.230us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 220.597us 20 20 100.00
V2 TOTAL 2236 2290 97.64
V2S tl_intg_err entropy_src_sec_cm 4.000s 111.489us 5 5 100.00
entropy_src_tl_intg_err 7.000s 296.612us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.650m 10.087ms 298 300 99.33
entropy_src_cfg_regwen 3.000s 15.189us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.650m 10.087ms 298 300 99.33
V2S sec_cm_config_redun entropy_src_rng 4.650m 10.087ms 298 300 99.33
V2S sec_cm_intersig_mubi entropy_src_rng 4.650m 10.087ms 298 300 99.33
entropy_src_fw_ov 2.350m 5.063ms 292 300 97.33
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 9.733m 10.013ms 971 1000 97.10
entropy_src_sec_cm 4.000s 111.489us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 9.733m 10.013ms 971 1000 97.10
entropy_src_sec_cm 4.000s 111.489us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.650m 10.087ms 298 300 99.33
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 9.733m 10.013ms 971 1000 97.10
entropy_src_sec_cm 4.000s 111.489us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 9.733m 10.013ms 971 1000 97.10
entropy_src_sec_cm 4.000s 111.489us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 9.733m 10.013ms 971 1000 97.10
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 4.000s 81.967us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 7.000s 296.612us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.400m 10.023ms 49 50 98.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 49 50 98.00
Unmapped tests entropy_src_intr 20.000s 3.013ms 44 50 88.00
TOTAL 2509 2570 97.63

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 0 0.00
V1 6 6 6 100.00
V2 11 11 7 63.64
V2S 3 3 3 100.00
V3 2 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
97.14 98.19 95.43 98.36 95.79 96.62 96.88 90.48 95.81

Failure Buckets

Past Results