ENTROPY_SRC Simulation Results

Thursday July 04 2024 23:02:28 UTC

GitHub Revision: 3e678c112b

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 94940390549829454688103081328166376218078465228811124044523808815554354133843

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 18.000s 33.712us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 3.000s 75.312us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 4.000s 21.891us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 15.000s 2.372ms 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 9.000s 1.059ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 4.000s 26.553us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 4.000s 21.891us 20 20 100.00
entropy_src_csr_aliasing 9.000s 1.059ms 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 18.000s 33.712us 50 50 100.00
entropy_src_rng 4.567m 10.017ms 299 300 99.67
entropy_src_fw_ov 2.567m 5.019ms 290 300 96.67
V2 firmware_mode entropy_src_fw_ov 2.567m 5.019ms 290 300 96.67
V2 rng_mode entropy_src_rng 4.567m 10.017ms 299 300 99.67
V2 rng_max_rate entropy_src_rng_max_rate 8.967m 10.015ms 399 400 99.75
V2 health_checks entropy_src_rng 4.567m 10.017ms 299 300 99.67
V2 conditioning entropy_src_rng 4.567m 10.017ms 299 300 99.67
V2 interrupts entropy_src_rng 4.567m 10.017ms 299 300 99.67
V2 alerts entropy_src_rng 4.567m 10.017ms 299 300 99.67
entropy_src_functional_alerts 9.000s 101.974us 50 50 100.00
V2 stress_all entropy_src_stress_all 16.000s 213.575us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 9.167m 10.013ms 970 1000 97.00
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 23.000s 1.312ms 50 50 100.00
V2 intr_test entropy_src_intr_test 4.000s 19.409us 50 50 100.00
V2 alert_test entropy_src_alert_test 17.000s 15.803us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 7.000s 708.482us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 7.000s 708.482us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 3.000s 75.312us 5 5 100.00
entropy_src_csr_rw 4.000s 21.891us 20 20 100.00
entropy_src_csr_aliasing 9.000s 1.059ms 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 214.789us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 3.000s 75.312us 5 5 100.00
entropy_src_csr_rw 4.000s 21.891us 20 20 100.00
entropy_src_csr_aliasing 9.000s 1.059ms 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 214.789us 20 20 100.00
V2 TOTAL 2248 2290 98.17
V2S tl_intg_err entropy_src_sec_cm 8.000s 53.890us 5 5 100.00
entropy_src_tl_intg_err 7.000s 766.735us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.567m 10.017ms 299 300 99.67
entropy_src_cfg_regwen 8.000s 38.015us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.567m 10.017ms 299 300 99.67
V2S sec_cm_config_redun entropy_src_rng 4.567m 10.017ms 299 300 99.67
V2S sec_cm_intersig_mubi entropy_src_rng 4.567m 10.017ms 299 300 99.67
entropy_src_fw_ov 2.567m 5.019ms 290 300 96.67
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 9.167m 10.013ms 970 1000 97.00
entropy_src_sec_cm 8.000s 53.890us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 9.167m 10.013ms 970 1000 97.00
entropy_src_sec_cm 8.000s 53.890us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.567m 10.017ms 299 300 99.67
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 9.167m 10.013ms 970 1000 97.00
entropy_src_sec_cm 8.000s 53.890us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 9.167m 10.013ms 970 1000 97.00
entropy_src_sec_cm 8.000s 53.890us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 9.167m 10.013ms 970 1000 97.00
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 9.000s 101.974us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 7.000s 766.735us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.867m 10.017ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
Unmapped tests entropy_src_intr 22.000s 1.395ms 50 50 100.00
TOTAL 2528 2570 98.37

Testplan Progress

Items Total Written Passing Progress
N.A. 1 1 1 100.00
V1 6 6 6 100.00
V2 11 11 7 63.64
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
97.10 98.15 95.32 98.36 95.79 96.59 96.88 90.48 95.66

Failure Buckets

Past Results