ENTROPY_SRC Simulation Results

Friday July 05 2024 23:02:55 UTC

GitHub Revision: 9edf84e236

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 47623749544922802985321435118963335754001495105472137721881337469861493653463

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 0 50 0.00
V1 csr_hw_reset entropy_src_csr_hw_reset 4.000s 93.184us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 4.000s 58.139us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 17.000s 267.642us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 8.000s 1.007ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 8.000s 67.900us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 4.000s 58.139us 20 20 100.00
entropy_src_csr_aliasing 8.000s 1.007ms 5 5 100.00
V1 TOTAL 55 105 52.38
V2 firmware entropy_src_smoke 0 50 0.00
entropy_src_rng 0 300 0.00
entropy_src_fw_ov 0 300 0.00
V2 firmware_mode entropy_src_fw_ov 0 300 0.00
V2 rng_mode entropy_src_rng 0 300 0.00
V2 rng_max_rate entropy_src_rng_max_rate 0 400 0.00
V2 health_checks entropy_src_rng 0 300 0.00
V2 conditioning entropy_src_rng 0 300 0.00
V2 interrupts entropy_src_rng 0 300 0.00
entropy_src_intr 0 50 0.00
V2 alerts entropy_src_rng 0 300 0.00
entropy_src_functional_alerts 0 50 0.00
V2 stress_all entropy_src_stress_all 0 50 0.00
V2 functional_errors entropy_src_functional_errors 0 1000 0.00
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 0 50 0.00
V2 intr_test entropy_src_intr_test 8.000s 21.513us 50 50 100.00
V2 alert_test entropy_src_alert_test 0 50 0.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 7.000s 159.681us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 7.000s 159.681us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 4.000s 93.184us 5 5 100.00
entropy_src_csr_rw 4.000s 58.139us 20 20 100.00
entropy_src_csr_aliasing 8.000s 1.007ms 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 80.748us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 4.000s 93.184us 5 5 100.00
entropy_src_csr_rw 4.000s 58.139us 20 20 100.00
entropy_src_csr_aliasing 8.000s 1.007ms 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 80.748us 20 20 100.00
V2 TOTAL 90 2340 3.85
V2S tl_intg_err entropy_src_sec_cm 0 5 0.00
entropy_src_tl_intg_err 9.000s 395.503us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 0 300 0.00
entropy_src_cfg_regwen 0 50 0.00
V2S sec_cm_config_mubi entropy_src_rng 0 300 0.00
V2S sec_cm_config_redun entropy_src_rng 0 300 0.00
V2S sec_cm_intersig_mubi entropy_src_rng 0 300 0.00
entropy_src_fw_ov 0 300 0.00
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 0 1000 0.00
entropy_src_sec_cm 0 5 0.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 0 1000 0.00
entropy_src_sec_cm 0 5 0.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 0 300 0.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 0 1000 0.00
entropy_src_sec_cm 0 5 0.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 0 1000 0.00
entropy_src_sec_cm 0 5 0.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 0 1000 0.00
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 0 50 0.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 9.000s 395.503us 20 20 100.00
V2S TOTAL 20 75 26.67
V3 external_health_tests entropy_src_rng_with_xht_rsps 0 50 0.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 0 50 0.00
TOTAL 165 2570 6.42

Testplan Progress

Items Total Written Passing Progress
V1 6 6 5 83.33
V2 12 12 3 25.00
V2S 3 3 1 33.33
V3 2 1 0 0.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
70.34 94.79 86.23 98.46 98.57 48.83 -- 100.00 7.59

Failure Buckets

Past Results