FLASH_CTRL Simulation Results

Saturday May 20 2023 07:05:26 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2781625531

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	4.145m	678.437us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.450s	41.459us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	45.070s	178.395us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.540s	194.315us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	55.890s	3.505ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.262m	6.847ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.550s	121.119us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.540s	194.315us	20	20	100.00
		flash_ctrl_csr_aliasing	1.262m	6.847ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.250s	16.311us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.400s	17.218us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.590s	89.352us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.099m	261.896us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	29.455m	334.101ms	2	3	66.67
		flash_ctrl_hw_rma_reset	19.262m	760.394ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.730s	26.403us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	47.330m	1.697s	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.533m	6.975ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	5.147m	4.106ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	58.764m	203.470ms	4	5	80.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	4.292m	8.047ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	38.350s	473.901us	40	40	100.00
		flash_ctrl_rw_evict_all_en	37.560s	229.435us	39	40	97.50
		flash_ctrl_re_evict	41.040s	333.813us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	8.069m	774.944us	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	8.069m	774.944us	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	16.938m	13.822ms	19	20	95.00
V2	fetch_code	flash_ctrl_fetch_code	25.790s	799.856us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	21.659m	2.491ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	45.892m	46.946ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	18.331m	8.258ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	48.487m	564.087us	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.520s	45.855us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	6.022m	2.665ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.860s	208.249us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.160s	233.869us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	29.928m	863.043us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.167m	3.067ms	50	50	100.00
		flash_ctrl_otp_reset	2.304m	39.238us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	29.455m	334.101ms	2	3	66.67
V2	interrupts	flash_ctrl_intr_rd	6.496m	3.803ms	40	40	100.00
		flash_ctrl_intr_wr	2.097m	9.857ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	10.768m	48.920ms	39	40	97.50
		flash_ctrl_intr_wr_slow_flash	9.135m	96.880ms	9	10	90.00
V2	invalid_op	flash_ctrl_invalid_op	1.601m	4.420ms	17	20	85.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	32.640s	686.505us	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.800s	60.231us	5	5	100.00
		flash_ctrl_ro_derr	6.439m	3.631ms	10	10	100.00
		flash_ctrl_rw_derr	29.002m	16.062ms	10	10	100.00
		flash_ctrl_derr_detect	1.861m	143.426us	5	5	100.00
		flash_ctrl_integrity	31.338m	29.486ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.860s	24.006us	5	5	100.00
		flash_ctrl_ro_serr	5.639m	8.863ms	10	10	100.00
		flash_ctrl_rw_serr	25.441m	13.037ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.577m	16.677ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.236m	630.536us	5	5	100.00
V2	scramble	flash_ctrl_wo	3.457m	2.527ms	20	20	100.00
		flash_ctrl_write_word_sweep	17.270s	181.746us	1	1	100.00
		flash_ctrl_read_word_sweep	13.180s	93.844us	1	1	100.00
		flash_ctrl_ro	4.534m	7.918ms	20	20	100.00
		flash_ctrl_rw	23.826m	22.132ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	37.190s	299.667us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	13.159m	41.318ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.045m	10.006ms	18	20	90.00
V2	alert_test	flash_ctrl_alert_test	14.580s	111.738us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.560s	58.415us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	19.700s	52.891us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	19.700s	52.891us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	45.070s	178.395us	5	5	100.00
		flash_ctrl_csr_rw	17.540s	194.315us	20	20	100.00
		flash_ctrl_csr_aliasing	1.262m	6.847ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.580s	672.878us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	45.070s	178.395us	5	5	100.00
		flash_ctrl_csr_rw	17.540s	194.315us	20	20	100.00
		flash_ctrl_csr_aliasing	1.262m	6.847ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.580s	672.878us	20	20	100.00
V2		TOTAL			1002	1013	98.91
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	1.721m	241.651us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	1.721m	241.651us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	1.721m	241.651us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	1.721m	241.651us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	1.760m	106.529us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.363h	5.134ms	5	5	100.00
		flash_ctrl_tl_intg_err	14.986m	581.515us	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	14.986m	581.515us	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	14.986m	581.515us	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.390s	120.963us	1	3	33.33
		flash_ctrl_wr_intg	14.860s	49.799us	2	3	66.67
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	4.145m	678.437us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.304m	39.238us	80	80	100.00
		flash_ctrl_disable	22.860s	208.249us	50	50	100.00
		flash_ctrl_sec_info_access	1.467m	14.646ms	50	50	100.00
		flash_ctrl_connect	16.160s	233.869us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.240s	61.181us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.540s	194.315us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	1.721m	241.651us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.540s	194.315us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	1.721m	241.651us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.540s	194.315us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	1.721m	241.651us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.860s	208.249us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.390s	120.963us	1	3	33.33
		flash_ctrl_access_after_disable	13.890s	33.219us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.860s	208.249us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	25.790s	799.856us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	23.826m	22.132ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	25.441m	13.037ms	10	10	100.00
		flash_ctrl_rw_derr	29.002m	16.062ms	10	10	100.00
		flash_ctrl_integrity	31.338m	29.486ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	29.455m	334.101ms	2	3	66.67
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.363h	5.134ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.363h	5.134ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.363h	5.134ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.363h	5.134ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	14.430s	21.052us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	13.880s	16.264us	1	5	20.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	13.840s	135.864us	4	5	80.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.363h	5.134ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.363h	5.134ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.363h	5.134ms	5	5	100.00
V2S		TOTAL			136	144	94.44
V3	asymmetric_read_path	flash_ctrl_rd_ooo	45.190s	129.844us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1259	1278	98.51

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	47	85.45
V2S	12	12	8	66.67
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.49	95.48	94.18	98.95	92.52	97.25	98.30	98.75

Failure Buckets

Offending '(!$isunknown(mem_tl_o.d_valid))' has 4 failures:

Test flash_ctrl_phy_host_grant_err has 4 failures.

0.flash_ctrl_phy_host_grant_err.1409896304
Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_phy_host_grant_err/latest/run.log

      Offending '(!$isunknown(mem_tl_o.d_valid))'
  UVM_ERROR @ 5599.2 ns: (flash_ctrl.sv:1397) [ASSERT FAILED] MemTlDValidKnownO_A
  UVM_INFO @ 5599.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_phy_host_grant_err.2385619117
Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_phy_host_grant_err/latest/run.log

      Offending '(!$isunknown(mem_tl_o.d_valid))'
  UVM_ERROR @ 4863.9 ns: (flash_ctrl.sv:1397) [ASSERT FAILED] MemTlDValidKnownO_A
  UVM_INFO @ 4863.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (flash_ctrl_rd_path_intg_vseq.sv:59) [flash_ctrl_rd_path_intg_vseq] Check failed saw_err == * (* [*] vs * [*]) has 2 failures:

Test flash_ctrl_rd_intg has 2 failures.

0.flash_ctrl_rd_intg.1054809658
Line 278, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rd_intg/latest/run.log

  UVM_ERROR @ 120963.1 ns: (flash_ctrl_rd_path_intg_vseq.sv:59) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rd_path_intg_vseq] Check failed saw_err == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 120963.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_rd_intg.3531345297
Line 270, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rd_intg/latest/run.log

  UVM_ERROR @ 26057.5 ns: (flash_ctrl_rd_path_intg_vseq.sv:59) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rd_path_intg_vseq] Check failed saw_err == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 26057.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:221) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 2 failures:

Test flash_ctrl_invalid_op has 2 failures.

1.flash_ctrl_invalid_op.248249975
Line 5174, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_invalid_op/latest/run.log

  UVM_ERROR @ 3426243.5 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 3426243.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

16.flash_ctrl_invalid_op.2404583410
Line 4588, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_invalid_op/latest/run.log

  UVM_ERROR @ 2925042.8 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 2925042.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (flash_phy_prim_monitor.sv:44) [monitor] timeout waiting for mon_start has 2 failures:
- Test flash_ctrl_intr_wr_slow_flash has 1 failures.
  - 9.flash_ctrl_intr_wr_slow_flash.3618102301
    Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_intr_wr_slow_flash/latest/run.log
```
  UVM_FATAL @ 200000.0 ns: (flash_phy_prim_monitor.sv:44) [uvm_test_top.env.m_fpp_agent.monitor] timeout waiting for mon_start
  UVM_INFO @ 200000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_intr_rd_slow_flash has 1 failures.
  - 39.flash_ctrl_intr_rd_slow_flash.2210661151
    Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/39.flash_ctrl_intr_rd_slow_flash/latest/run.log
```
  UVM_FATAL @ 200000.0 ns: (flash_phy_prim_monitor.sv:44) [uvm_test_top.env.m_fpp_agent.monitor] timeout waiting for mon_start
  UVM_INFO @ 200000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test flash_ctrl_full_mem_access has 1 failures.
  - 0.flash_ctrl_full_mem_access.3725415436
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_full_mem_access/latest/run.log
```
  Job ID: smart:9b884279-1cc1-4484-9103-4c0da15c1dd2
```

Offending '$fell(src_ack_o)' has 1 failures:

Test flash_ctrl_hw_rma has 1 failures.

1.flash_ctrl_hw_rma.2667005473
Line 333, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_hw_rma/latest/run.log

      Offending '$fell(src_ack_o)'
  UVM_ERROR @ 176404524.9 ns: (prim_sync_reqack.sv:349) [ASSERT FAILED] SyncReqAckHoldReq
  UVM_INFO @ 176404524.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:365) [wdata_page0_comp_bank0] *: obs:exp *_*_dfbdf098_ec1b70c4:2b_*_b7253046_f* mismatch!! has 1 failures:
- Test flash_ctrl_wr_intg has 1 failures.
  - 2.flash_ctrl_wr_intg.2610259516
    Line 278, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_wr_intg/latest/run.log
```
  UVM_ERROR @ 68531.6 ns: (flash_ctrl_otf_scoreboard.sv:365) [wdata_page0_comp_bank0]    0: obs:exp    65_8_dfbdf098_ec1b70c4:2b_2_b7253046_f1412507  mismatch!!
  UVM_INFO @ 68531.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:479) [lm_wdata_comp_bank0] Check failed rcv.mem_addr == exp.req.addr (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_hw_prog_rma_wipe_err has 1 failures.
  - 2.flash_ctrl_hw_prog_rma_wipe_err.2801000640
    Line 269, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_hw_prog_rma_wipe_err/latest/run.log
```
  UVM_ERROR @ 10075697.1 ns: (flash_ctrl_otf_scoreboard.sv:479) [lm_wdata_comp_bank0] Check failed rcv.mem_addr == exp.req.addr (0 [0x0] vs 5915 [0x171b])
  UVM_INFO @ 10075697.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:221) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_std_err triggered unexpectedly has 1 failures:
- Test flash_ctrl_phy_ack_consistency has 1 failures.
  - 4.flash_ctrl_phy_ack_consistency.4132509094
    Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_phy_ack_consistency/latest/run.log
```
  UVM_ERROR @ 14867.1 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_std_err triggered unexpectedly
  UVM_INFO @ 14867.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:221) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly has 1 failures:
- Test flash_ctrl_invalid_op has 1 failures.
  - 8.flash_ctrl_invalid_op.3212098665
    Line 506, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_invalid_op/latest/run.log
```
  UVM_ERROR @ 96534.8 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
  UVM_INFO @ 96534.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict_all_en has 1 failures.
  - 12.flash_ctrl_rw_evict_all_en.963311112
    Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 18578.1 ns: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 18578.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_ctrl_mp_regions_vseq.sv:196) [flash_ctrl_mp_regions_vseq] wait timeout for alert_count == exp_alertcnt after do_mp_reg() alert_cnt:* exp_alert_cnt:* has 1 failures:
- Test flash_ctrl_mp_regions has 1 failures.
  - 15.flash_ctrl_mp_regions.577424646
    Line 410, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_mp_regions/latest/run.log
```
  UVM_FATAL @ 1050197.5 ns: (flash_ctrl_mp_regions_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.flash_ctrl_mp_regions_vseq] wait timeout for alert_count == exp_alertcnt after do_mp_reg() alert_cnt:5  exp_alert_cnt:6
  UVM_INFO @ 1050197.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:479) [lm_wdata_comp_bank1] Check failed rcv.mem_addr == exp.req.addr (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_hw_prog_rma_wipe_err has 1 failures.
  - 16.flash_ctrl_hw_prog_rma_wipe_err.3281299144
    Line 269, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_hw_prog_rma_wipe_err/latest/run.log
```
  UVM_ERROR @ 10005778.3 ns: (flash_ctrl_otf_scoreboard.sv:479) [lm_wdata_comp_bank1] Check failed rcv.mem_addr == exp.req.addr (0 [0x0] vs 28899 [0x70e3])
  UVM_INFO @ 10005778.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```