FLASH_CTRL Simulation Results

Sunday January 07 2024 20:02:41 UTC

GitHub Revision: `042415198f`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 94802583296605211241780338187580260959003534163885373932116464911642413280689

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	4.216m	1.383ms	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.320s	16.224us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	45.940s	373.244us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.740s	311.742us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.435m	9.092ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.169m	1.779ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.270s	35.672us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.740s	311.742us	20	20	100.00
		flash_ctrl_csr_aliasing	1.169m	1.779ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.390s	15.064us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.750s	110.273us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.800s	28.456us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.091m	128.794us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	31.017m	129.775ms	3	3	100.00
		flash_ctrl_hw_rma_reset	14.314m	160.176ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.690s	15.527us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	44.441m	1.091s	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	7.448m	15.006ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	42.190s	928.791us	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	43.027m	330.819ms	4	5	80.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	3.243m	1.385ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	35.150s	91.695us	40	40	100.00
		flash_ctrl_rw_evict_all_en	36.600s	124.993us	40	40	100.00
		flash_ctrl_re_evict	39.710s	141.712us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	8.997m	3.336ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	8.997m	3.336ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	12.075m	36.050ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	28.980s	422.199us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	21.159m	447.723us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	39.393m	4.973ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	17.871m	438.791us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	47.347m	632.614us	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.560s	150.977us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.223m	1.449ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.870s	61.768us	44	50	88.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.340s	14.435us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	15.900m	231.378us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	3.898m	45.608ms	50	50	100.00
		flash_ctrl_otp_reset	2.245m	67.218us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	31.017m	129.775ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	3.096m	3.523ms	40	40	100.00
		flash_ctrl_intr_wr	1.879m	19.570ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	4.222m	23.510ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	11.377m	191.528ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.492m	4.412ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.242m	1.908ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.100s	60.337us	5	5	100.00
		flash_ctrl_ro_derr	2.667m	3.297ms	10	10	100.00
		flash_ctrl_rw_derr	9.938m	52.988ms	10	10	100.00
		flash_ctrl_derr_detect	1.776m	124.343us	5	5	100.00
		flash_ctrl_integrity	10.662m	59.662ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.350s	307.827us	5	5	100.00
		flash_ctrl_ro_serr	2.408m	5.942ms	10	10	100.00
		flash_ctrl_rw_serr	10.843m	3.787ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.569m	7.696ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.587m	2.022ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.647m	9.477ms	20	20	100.00
		flash_ctrl_write_word_sweep	16.930s	285.535us	1	1	100.00
		flash_ctrl_read_word_sweep	13.740s	17.529us	1	1	100.00
		flash_ctrl_ro	1.786m	5.198ms	20	20	100.00
		flash_ctrl_rw	10.535m	29.179ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	36.410s	665.829us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	14.134m	134.608ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	4.860m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.190s	207.104us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.410s	30.140us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.230s	420.985us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.230s	420.985us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	45.940s	373.244us	5	5	100.00
		flash_ctrl_csr_rw	17.740s	311.742us	20	20	100.00
		flash_ctrl_csr_aliasing	1.169m	1.779ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.330s	318.263us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	45.940s	373.244us	5	5	100.00
		flash_ctrl_csr_rw	17.740s	311.742us	20	20	100.00
		flash_ctrl_csr_aliasing	1.169m	1.779ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.330s	318.263us	20	20	100.00
V2		TOTAL			1006	1013	99.31
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	15.870s	19.550us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	15.870s	19.550us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	15.870s	19.550us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	15.870s	19.550us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.030s	34.845us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.304h	4.157ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.152m	2.940ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.152m	2.940ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.152m	2.940ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.050s	555.546us	3	3	100.00
		flash_ctrl_wr_intg	15.290s	172.574us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	4.216m	1.383ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.245m	67.218us	80	80	100.00
		flash_ctrl_disable	22.870s	61.768us	44	50	88.00
		flash_ctrl_sec_info_access	2.000m	41.924ms	50	50	100.00
		flash_ctrl_connect	16.340s	14.435us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	13.910s	33.302us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.740s	311.742us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.870s	19.550us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.740s	311.742us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.870s	19.550us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.740s	311.742us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	15.870s	19.550us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.870s	61.768us	44	50	88.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.050s	555.546us	3	3	100.00
		flash_ctrl_access_after_disable	13.770s	13.696us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.870s	61.768us	44	50	88.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	28.980s	422.199us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	10.535m	29.179ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	10.843m	3.787ms	10	10	100.00
		flash_ctrl_rw_derr	9.938m	52.988ms	10	10	100.00
		flash_ctrl_integrity	10.662m	59.662ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	31.017m	129.775ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.304h	4.157ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.304h	4.157ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.304h	4.157ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.304h	4.157ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	17.700s	85.354us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.050s	14.706us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.360s	46.545us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.304h	4.157ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.304h	4.157ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.304h	4.157ms	5	5	100.00
V2S		TOTAL			144	144	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	45.440s	70.359us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1271	1278	99.45

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	53	96.36
V2S	12	12	12	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.44	95.31	93.98	98.95	92.52	97.21	98.62	98.49

Failure Buckets

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
- Test flash_ctrl_full_mem_access has 1 failures.
  - 2.flash_ctrl_full_mem_access.13390887079354958541924810312536717283638589687672078557304930304492282567098
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_full_mem_access/latest/run.log
```
  Job ID: smart:35dcef5f-4b66-4d2c-bf15-584a1aca0eac
```
- Test flash_ctrl_disable has 3 failures.
  - 31.flash_ctrl_disable.47964178726694036336999345041068833987086935630823617980346562131936576333481
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/31.flash_ctrl_disable/latest/run.log
```
  Job ID: smart:0869bc68-fc5f-4071-98f1-9b85ea89ce6d
```
  - 34.flash_ctrl_disable.36292356599775680566459183890305059179974323883859869789090976319828874501261
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/34.flash_ctrl_disable/latest/run.log
```
  Job ID: smart:0964d270-2174-458c-990a-cc0a7fbac7d9
```
  - ... and 1 more failures.

UVM_ERROR (cip_base_scoreboard.sv:455) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@79322) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_disable has 1 failures.

14.flash_ctrl_disable.50519641677271217780905272323425311787812901897514051623533018968055841849270
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_disable/latest/run.log

  UVM_ERROR @ 9628.7 ns: (cip_base_scoreboard.sv:455) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@79322) { a_addr: 'hc3a1c  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'ha8  a_opcode: 'h4  a_user: 'h2532a  d_param: 'h0  d_source: 'ha8  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 9628.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:455) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@79614) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_disable has 1 failures.

25.flash_ctrl_disable.12254845358681996761339062415845596651402807411849404818356891341066212464997
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/25.flash_ctrl_disable/latest/run.log

  UVM_ERROR @ 10445.5 ns: (cip_base_scoreboard.sv:455) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@79614) { a_addr: 'hadf20  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h95  a_opcode: 'h4  a_user: 'h2752a  d_param: 'h0  d_source: 'h95  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 10445.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:455) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@84365) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_disable has 1 failures.

44.flash_ctrl_disable.25363117775693110180017739654632552750102317639377137519885399102797409790666
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/44.flash_ctrl_disable/latest/run.log

  UVM_ERROR @ 18006.3 ns: (cip_base_scoreboard.sv:455) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@84365) { a_addr: 'h5b98  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h26  a_opcode: 'h4  a_user: 'h2402a  d_param: 'h0  d_source: 'h26  d_data: 'hffffffff  d_size: 'h2  d_opcode: 'h1  d_error: 'h1  d_sink: 'h0  d_user: 'heaa  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 18006.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---