FLASH_CTRL Simulation Results

Sunday February 18 2024 20:02:30 UTC

GitHub Revision: `8faf04697a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 18983509472502570446328716692660256492766541929441074968843370054317032656232

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.318m	106.881us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.640s	55.136us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.110s	130.889us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.750s	55.192us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.180m	4.774ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.140m	4.966ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	25.180s	217.820us	18	20	90.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.750s	55.192us	20	20	100.00
		flash_ctrl_csr_aliasing	1.140m	4.966ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.700s	17.918us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.590s	50.989us	5	5	100.00
V1		TOTAL			118	120	98.33
V2	sw_op	flash_ctrl_sw_op	26.930s	20.651us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.153m	93.483us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	33.056m	143.256ms	3	3	100.00
		flash_ctrl_hw_rma_reset	21.545m	760.455ms	12	20	60.00
		flash_ctrl_lcmgr_intg	14.180s	67.010us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	40.638m	386.372ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.467m	53.942ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	4.553m	7.214ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	46.265m	191.202ms	2	5	40.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.541m	734.842us	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	38.580s	132.478us	40	40	100.00
		flash_ctrl_rw_evict_all_en	39.340s	228.258us	40	40	100.00
		flash_ctrl_re_evict	41.700s	528.448us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	12.029m	20.984ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	12.029m	20.984ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	19.814m	17.892ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	30.880s	1.472ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	24.073m	3.249ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	41.039m	71.363ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	15.454m	871.050us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	50.058m	9.684ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.240s	33.640us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.435m	2.623ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	9.784m	10.005ms	28	50	56.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.980s	187.042us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	32.345m	1.355ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.444m	3.024ms	50	50	100.00
		flash_ctrl_otp_reset	2.345m	43.726us	41	80	51.25
V2	isolation_partition	flash_ctrl_hw_rma	33.056m	143.256ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	3.642m	5.520ms	40	40	100.00
		flash_ctrl_intr_wr	2.104m	5.161ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	4.597m	8.986ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	13.265m	221.914ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.701m	9.843ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.273m	1.745ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.110s	31.480us	5	5	100.00
		flash_ctrl_ro_derr	2.731m	697.805us	10	10	100.00
		flash_ctrl_rw_derr	11.615m	30.480ms	10	10	100.00
		flash_ctrl_derr_detect	1.817m	504.832us	5	5	100.00
		flash_ctrl_integrity	10.898m	7.310ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.290s	42.146us	5	5	100.00
		flash_ctrl_ro_serr	2.852m	5.333ms	10	10	100.00
		flash_ctrl_rw_serr	12.076m	14.030ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.414m	910.936us	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.225m	1.364ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.780m	5.319ms	20	20	100.00
		flash_ctrl_write_word_sweep	14.360s	227.114us	1	1	100.00
		flash_ctrl_read_word_sweep	13.620s	20.636us	1	1	100.00
		flash_ctrl_ro	2.239m	1.796ms	20	20	100.00
		flash_ctrl_rw	11.518m	4.148ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	39.420s	304.354us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	15.617m	101.396ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.058m	10.013ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.730s	39.495us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.910s	23.673us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	19.810s	63.227us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	19.810s	63.227us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.110s	130.889us	5	5	100.00
		flash_ctrl_csr_rw	17.750s	55.192us	20	20	100.00
		flash_ctrl_csr_aliasing	1.140m	4.966ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.290s	412.041us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.110s	130.889us	5	5	100.00
		flash_ctrl_csr_rw	17.750s	55.192us	20	20	100.00
		flash_ctrl_csr_aliasing	1.140m	4.966ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.290s	412.041us	20	20	100.00
V2		TOTAL			941	1013	92.89
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	15.860s	22.461us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	15.860s	22.461us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	15.860s	22.461us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	15.860s	22.461us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.130s	43.227us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.360h	4.007ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.206m	7.826ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.206m	7.826ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.206m	7.826ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.260s	208.195us	3	3	100.00
		flash_ctrl_wr_intg	15.020s	400.533us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.318m	106.881us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.345m	43.726us	41	80	51.25
		flash_ctrl_disable	9.784m	10.005ms	28	50	56.00
		flash_ctrl_sec_info_access	1.641m	15.464ms	50	50	100.00
		flash_ctrl_connect	16.980s	187.042us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.310s	21.041us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.750s	55.192us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.860s	22.461us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.750s	55.192us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.860s	22.461us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.750s	55.192us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	15.860s	22.461us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	9.784m	10.005ms	28	50	56.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.260s	208.195us	3	3	100.00
		flash_ctrl_access_after_disable	13.710s	13.891us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	9.784m	10.005ms	28	50	56.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	30.880s	1.472ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.518m	4.148ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	12.076m	14.030ms	10	10	100.00
		flash_ctrl_rw_derr	11.615m	30.480ms	10	10	100.00
		flash_ctrl_integrity	10.898m	7.310ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	33.056m	143.256ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.360h	4.007ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.360h	4.007ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.360h	4.007ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.360h	4.007ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	1.347m	864.911us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.780s	14.721us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.220s	15.458us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.360h	4.007ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.360h	4.007ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.360h	4.007ms	5	5	100.00
V2S		TOTAL			144	144	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	45.150s	143.724us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1204	1278	94.21

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	8	88.89
V2	55	55	51	92.73
V2S	12	12	12	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.10	95.33	94.10	98.95	90.48	97.16	98.30	98.40

Failure Buckets

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'val' while register 'flash_ctrl_core_reg_block.dis' is being accessed has 67 failures:

Test flash_ctrl_hw_rma_reset has 8 failures.

0.flash_ctrl_hw_rma_reset.53834184298610180389179539552309973011791751668074716759538372151594194746454
Line 291, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_hw_rma_reset/latest/run.log

  UVM_WARNING @ 19934.2 ns: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'val' while register 'flash_ctrl_core_reg_block.dis' is being accessed
  UVM_INFO @ 20288.4 ns: (flash_ctrl_hw_rma_reset_vseq.sv:73) uvm_test_top.env.virtual_sequencer [Test] RESET
  UVM_INFO @ 23089.8 ns: (flash_mem_bkdr_util.sv:26) [mem_bkdr_util[FlashPartData][0]] Randomizing flash mem contents
  UVM_INFO @ 23089.8 ns: (flash_mem_bkdr_util.sv:26) [mem_bkdr_util[FlashPartData][1]] Randomizing flash mem contents
  UVM_INFO @ 23089.8 ns: (flash_mem_bkdr_util.sv:26) [mem_bkdr_util[FlashPartInfo][0]] Randomizing flash mem contents

3.flash_ctrl_hw_rma_reset.12995462674806810167199568497340141952450385195097308790636753805213220947834
Line 291, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_hw_rma_reset/latest/run.log

  UVM_WARNING @ 8786.5 ns: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'val' while register 'flash_ctrl_core_reg_block.dis' is being accessed
  UVM_INFO @ 9006.5 ns: (flash_ctrl_hw_rma_reset_vseq.sv:73) uvm_test_top.env.virtual_sequencer [Test] RESET
  UVM_INFO @ 10686.5 ns: (flash_mem_bkdr_util.sv:26) [mem_bkdr_util[FlashPartData][0]] Randomizing flash mem contents
  UVM_INFO @ 10686.5 ns: (flash_mem_bkdr_util.sv:26) [mem_bkdr_util[FlashPartData][1]] Randomizing flash mem contents
  UVM_INFO @ 10686.5 ns: (flash_mem_bkdr_util.sv:26) [mem_bkdr_util[FlashPartInfo][0]] Randomizing flash mem contents

... and 6 more failures.

Test flash_ctrl_otp_reset has 39 failures.

0.flash_ctrl_otp_reset.479503743211598190780384172324374655983249000689314193616381794762559288352
Line 316, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_otp_reset/latest/run.log

  UVM_WARNING @ 8324.0 ns: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'val' while register 'flash_ctrl_core_reg_block.dis' is being accessed
  UVM_INFO @ 8436.2 ns: (flash_ctrl_otp_reset_vseq.sv:131) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.flash_ctrl_otp_reset_vseq] RESET
  UVM_INFO @ 9395.0 ns: (mem_bkdr_util.sv:529) [mem_bkdr_util[FlashPartData][0]] Set memory
  UVM_INFO @ 9395.0 ns: (mem_bkdr_util.sv:529) [mem_bkdr_util[FlashPartData][1]] Set memory
  UVM_INFO @ 9395.0 ns: (mem_bkdr_util.sv:529) [mem_bkdr_util[FlashPartInfo][0]] Set memory

1.flash_ctrl_otp_reset.64750022558312568271679380270230501991315983876605953393602780001685976128566
Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_otp_reset/latest/run.log

  UVM_WARNING @ 3855.4 ns: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'val' while register 'flash_ctrl_core_reg_block.dis' is being accessed
  UVM_INFO @ 3995.4 ns: (flash_ctrl_otp_reset_vseq.sv:131) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.flash_ctrl_otp_reset_vseq] RESET
  UVM_INFO @ 4865.4 ns: (mem_bkdr_util.sv:529) [mem_bkdr_util[FlashPartData][0]] Set memory
  UVM_INFO @ 4865.4 ns: (mem_bkdr_util.sv:529) [mem_bkdr_util[FlashPartData][1]] Set memory
  UVM_INFO @ 4865.4 ns: (mem_bkdr_util.sv:529) [mem_bkdr_util[FlashPartInfo][0]] Set memory

... and 37 more failures.

Test flash_ctrl_disable has 20 failures.

0.flash_ctrl_disable.44566455692878242880059603753288107084510040831837114934527111378324820275640
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_disable/latest/run.log

  UVM_WARNING @ 11611.5 ns: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'val' while register 'flash_ctrl_core_reg_block.dis' is being accessed
  UVM_INFO @ 17686.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.flash_ctrl_disable.101272382079175403367337008103745246716472909170575714694336664765157435605761
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_disable/latest/run.log

  UVM_WARNING @ 58289.5 ns: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'val' while register 'flash_ctrl_core_reg_block.dis' is being accessed
  UVM_INFO @ 66069.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 18 more failures.

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 5 failures:
- Test flash_ctrl_full_mem_access has 3 failures.
  - 0.flash_ctrl_full_mem_access.49847540622666747319562193828544434316471074707338629050607540904187455762489
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_full_mem_access/latest/run.log
```
  Job ID: smart:5b9d9deb-d679-408f-9506-6120cd719e81
```
  - 3.flash_ctrl_full_mem_access.74125130864311488143713711058357386035324124961997661662378258776219759015619
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_full_mem_access/latest/run.log
```
  Job ID: smart:5720f087-00b5-432d-8648-734c20d60953
```
  - ... and 1 more failures.
- Test flash_ctrl_disable has 2 failures.
  - 4.flash_ctrl_disable.24642475845088996740460938505846921022251352877975566510641589607992337096913
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_disable/latest/run.log
```
  Job ID: smart:1ba004c4-b333-44b6-818d-0d75bbc79aba
```
  - 33.flash_ctrl_disable.10720396791862912761814531266156905571459780329824305100292988857629756710029
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/33.flash_ctrl_disable/latest/run.log
```
  Job ID: smart:9488db8e-a186-452a-a1c3-d53c6b660ce8
```
UVM_ERROR (cip_base_vseq.sv:756) [flash_ctrl_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset. has 2 failures:
- Test flash_ctrl_csr_mem_rw_with_rand_reset has 2 failures.
  - 2.flash_ctrl_csr_mem_rw_with_rand_reset.104572461156423109055336046292481050517818050206602087017055230240241829347376
    Line 315, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 110141.4 ns: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 110141.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.flash_ctrl_csr_mem_rw_with_rand_reset.55881157218702576078608263008552732572860940328282201896313462351613120909274
    Line 298, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 906257.5 ns: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 906257.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```