4ddd81322f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | flash_ctrl_smoke | 0 | 50 | 0.00 | ||
| V1 | smoke_hw | flash_ctrl_smoke_hw | 0 | 5 | 0.00 | ||
| V1 | csr_hw_reset | flash_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | flash_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | flash_ctrl_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | flash_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | flash_ctrl_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | flash_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| flash_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| V1 | mem_walk | flash_ctrl_mem_walk | 0 | 5 | 0.00 | ||
| V1 | mem_partial_access | flash_ctrl_mem_partial_access | 0 | 5 | 0.00 | ||
| V1 | TOTAL | 0 | 120 | 0.00 | |||
| V2 | sw_op | flash_ctrl_sw_op | 0 | 5 | 0.00 | ||
| V2 | host_read_direct | flash_ctrl_host_dir_rd | 0 | 5 | 0.00 | ||
| V2 | rma_hw_if | flash_ctrl_hw_rma | 0 | 3 | 0.00 | ||
| flash_ctrl_hw_rma_reset | 0 | 20 | 0.00 | ||||
| flash_ctrl_lcmgr_intg | 0 | 20 | 0.00 | ||||
| V2 | host_controller_arb | flash_ctrl_host_ctrl_arb | 0 | 5 | 0.00 | ||
| V2 | erase_suspend | flash_ctrl_erase_suspend | 0 | 5 | 0.00 | ||
| V2 | program_reset | flash_ctrl_prog_reset | 0 | 30 | 0.00 | ||
| V2 | full_memory_access | flash_ctrl_full_mem_access | 0 | 5 | 0.00 | ||
| V2 | rd_buff_eviction | flash_ctrl_rd_buff_evict | 0 | 5 | 0.00 | ||
| V2 | rd_buff_eviction_w_ecc | flash_ctrl_rw_evict | 0 | 40 | 0.00 | ||
| flash_ctrl_rw_evict_all_en | 0 | 40 | 0.00 | ||||
| flash_ctrl_re_evict | 0 | 20 | 0.00 | ||||
| V2 | host_arb | flash_ctrl_phy_arb | 0 | 20 | 0.00 | ||
| V2 | host_interleave | flash_ctrl_phy_arb | 0 | 20 | 0.00 | ||
| V2 | memory_protection | flash_ctrl_mp_regions | 0 | 20 | 0.00 | ||
| V2 | fetch_code | flash_ctrl_fetch_code | 0 | 10 | 0.00 | ||
| V2 | all_partitions | flash_ctrl_rand_ops | 0 | 20 | 0.00 | ||
| V2 | error_mp | flash_ctrl_error_mp | 0 | 10 | 0.00 | ||
| V2 | error_prog_win | flash_ctrl_error_prog_win | 0 | 10 | 0.00 | ||
| V2 | error_prog_type | flash_ctrl_error_prog_type | 0 | 5 | 0.00 | ||
| V2 | error_read_seed | flash_ctrl_hw_read_seed_err | 0 | 20 | 0.00 | ||
| V2 | read_write_overflow | flash_ctrl_oversize_error | 0 | 5 | 0.00 | ||
| V2 | flash_ctrl_disable | flash_ctrl_disable | 0 | 50 | 0.00 | ||
| V2 | flash_ctrl_connect | flash_ctrl_connect | 0 | 80 | 0.00 | ||
| V2 | stress_all | flash_ctrl_stress_all | 0 | 5 | 0.00 | ||
| V2 | secret_partition | flash_ctrl_hw_sec_otp | 0 | 50 | 0.00 | ||
| flash_ctrl_otp_reset | 0 | 80 | 0.00 | ||||
| V2 | isolation_partition | flash_ctrl_hw_rma | 0 | 3 | 0.00 | ||
| V2 | interrupts | flash_ctrl_intr_rd | 0 | 40 | 0.00 | ||
| flash_ctrl_intr_wr | 0 | 10 | 0.00 | ||||
| flash_ctrl_intr_rd_slow_flash | 0 | 40 | 0.00 | ||||
| flash_ctrl_intr_wr_slow_flash | 0 | 10 | 0.00 | ||||
| V2 | invalid_op | flash_ctrl_invalid_op | 0 | 20 | 0.00 | ||
| V2 | mid_op_rst | flash_ctrl_mid_op_rst | 0 | 5 | 0.00 | ||
| V2 | double_bit_err | flash_ctrl_read_word_sweep_derr | 0 | 5 | 0.00 | ||
| flash_ctrl_ro_derr | 0 | 10 | 0.00 | ||||
| flash_ctrl_rw_derr | 0 | 10 | 0.00 | ||||
| flash_ctrl_derr_detect | 0 | 5 | 0.00 | ||||
| flash_ctrl_integrity | 0 | 5 | 0.00 | ||||
| V2 | single_bit_err | flash_ctrl_read_word_sweep_serr | 0 | 5 | 0.00 | ||
| flash_ctrl_ro_serr | 0 | 10 | 0.00 | ||||
| flash_ctrl_rw_serr | 0 | 10 | 0.00 | ||||
| V2 | singlebit_err_counter | flash_ctrl_serr_counter | 0 | 5 | 0.00 | ||
| V2 | singlebit_err_address | flash_ctrl_serr_address | 0 | 5 | 0.00 | ||
| V2 | scramble | flash_ctrl_wo | 0 | 20 | 0.00 | ||
| flash_ctrl_write_word_sweep | 0 | 1 | 0.00 | ||||
| flash_ctrl_read_word_sweep | 0 | 1 | 0.00 | ||||
| flash_ctrl_ro | 0 | 20 | 0.00 | ||||
| flash_ctrl_rw | 0 | 20 | 0.00 | ||||
| V2 | filesystem_support | flash_ctrl_fs_sup | 0 | 5 | 0.00 | ||
| V2 | rma_write_process_error | flash_ctrl_rma_err | 0 | 3 | 0.00 | ||
| flash_ctrl_hw_prog_rma_wipe_err | 0 | 20 | 0.00 | ||||
| V2 | alert_test | flash_ctrl_alert_test | 0 | 50 | 0.00 | ||
| V2 | intr_test | flash_ctrl_intr_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | flash_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | flash_ctrl_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | flash_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| flash_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| flash_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| flash_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | flash_ctrl_csr_hw_reset | 0 | 5 | 0.00 | ||
| flash_ctrl_csr_rw | 0 | 20 | 0.00 | ||||
| flash_ctrl_csr_aliasing | 0 | 5 | 0.00 | ||||
| flash_ctrl_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 1013 | 0.00 | |||
| V2S | shadow_reg_update_error | flash_ctrl_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_read_clear_staged_value | flash_ctrl_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_storage_error | flash_ctrl_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadowed_reset_glitch | flash_ctrl_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | shadow_reg_update_error_with_csr_rw | flash_ctrl_shadow_reg_errors_with_csr_rw | 0 | 20 | 0.00 | ||
| V2S | tl_intg_err | flash_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| flash_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_reg_bus_integrity | flash_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | sec_cm_host_bus_integrity | flash_ctrl_tl_intg_err | 0 | 20 | 0.00 | ||
| V2S | sec_cm_mem_bus_integrity | flash_ctrl_rd_intg | 0 | 3 | 0.00 | ||
| flash_ctrl_wr_intg | 0 | 3 | 0.00 | ||||
| V2S | sec_cm_scramble_key_sideload | flash_ctrl_smoke | 0 | 50 | 0.00 | ||
| V2S | sec_cm_lc_ctrl_intersig_mubi | flash_ctrl_otp_reset | 0 | 80 | 0.00 | ||
| flash_ctrl_disable | 0 | 50 | 0.00 | ||||
| flash_ctrl_sec_info_access | 0 | 50 | 0.00 | ||||
| flash_ctrl_connect | 0 | 80 | 0.00 | ||||
| V2S | sec_cm_ctrl_config_regwen | flash_ctrl_config_regwen | 0 | 5 | 0.00 | ||
| V2S | sec_cm_data_regions_config_regwen | flash_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| V2S | sec_cm_data_regions_config_shadow | flash_ctrl_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | sec_cm_info_regions_config_regwen | flash_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| V2S | sec_cm_info_regions_config_shadow | flash_ctrl_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | sec_cm_bank_config_regwen | flash_ctrl_csr_rw | 0 | 20 | 0.00 | ||
| V2S | sec_cm_bank_config_shadow | flash_ctrl_shadow_reg_errors | 0 | 20 | 0.00 | ||
| V2S | sec_cm_mem_ctrl_global_esc | flash_ctrl_disable | 0 | 50 | 0.00 | ||
| V2S | sec_cm_mem_ctrl_local_esc | flash_ctrl_rd_intg | 0 | 3 | 0.00 | ||
| flash_ctrl_access_after_disable | 0 | 3 | 0.00 | ||||
| V2S | sec_cm_mem_disable_config_mubi | flash_ctrl_disable | 0 | 50 | 0.00 | ||
| V2S | sec_cm_exec_config_redun | flash_ctrl_fetch_code | 0 | 10 | 0.00 | ||
| V2S | sec_cm_mem_scramble | flash_ctrl_rw | 0 | 20 | 0.00 | ||
| V2S | sec_cm_mem_integrity | flash_ctrl_rw_serr | 0 | 10 | 0.00 | ||
| flash_ctrl_rw_derr | 0 | 10 | 0.00 | ||||
| flash_ctrl_integrity | 0 | 5 | 0.00 | ||||
| V2S | sec_cm_rma_entry_mem_sec_wipe | flash_ctrl_hw_rma | 0 | 3 | 0.00 | ||
| V2S | sec_cm_ctrl_fsm_sparse | flash_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_phy_fsm_sparse | flash_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_phy_prog_fsm_sparse | flash_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_ctr_redun | flash_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_phy_arbiter_ctrl_redun | flash_ctrl_phy_arb_redun | 0 | 5 | 0.00 | ||
| V2S | sec_cm_phy_host_grant_ctrl_consistency | flash_ctrl_phy_host_grant_err | 0 | 5 | 0.00 | ||
| V2S | sec_cm_phy_ack_ctrl_consistency | flash_ctrl_phy_ack_consistency | 0 | 5 | 0.00 | ||
| V2S | sec_cm_fifo_ctr_redun | flash_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | flash_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | sec_cm_prog_tl_lc_gate_fsm_sparse | flash_ctrl_sec_cm | 0 | 5 | 0.00 | ||
| V2S | TOTAL | 0 | 144 | 0.00 | |||
| V3 | asymmetric_read_path | flash_ctrl_rd_ooo | 0 | 1 | 0.00 | ||
| V3 | stress_all_with_rand_reset | flash_ctrl_stress_all_with_rand_reset | 0 | 0 | -- | ||
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| TOTAL | 0 | 1278 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 0 | 0.00 |
| V2 | 55 | 55 | 0 | 0.00 |
| V2S | 12 | 12 | 0 | 0.00 |
| V3 | 2 | 1 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 1280 failures:
0.flash_ctrl_smoke.38672394723889755121171658688217655035911821285130283408728294924269191125144
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_smoke/latest/run.log
1.flash_ctrl_smoke.115128169648072726131266789763247759908500547449147242328382253295355213871549
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_smoke/latest/run.log
... and 48 more failures.
0.flash_ctrl_smoke_hw.53193139813777004711194990643737297753513724366767162451512827379530086623441
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_smoke_hw/latest/run.log
1.flash_ctrl_smoke_hw.25503657859356915883427497878801994724717839118598145968466854032501445270937
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_smoke_hw/latest/run.log
... and 3 more failures.
0.flash_ctrl_rand_ops.73388873069129379938049236012030996169890036749018982195993634986439967269430
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rand_ops/latest/run.log
1.flash_ctrl_rand_ops.108699227217043688067594175155640700471263334525918791776833594649553014517539
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rand_ops/latest/run.log
... and 18 more failures.
0.flash_ctrl_sw_op.78623627641813791343048191047016625165261177043865453735577119879353878866245
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_sw_op/latest/run.log
1.flash_ctrl_sw_op.9778458664770197574389104651031695239839153504860177998421800722490231628367
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_sw_op/latest/run.log
... and 3 more failures.
0.flash_ctrl_host_dir_rd.15647637338765603626289904785772556130433854685807624223513256562768563774984
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_host_dir_rd/latest/run.log
1.flash_ctrl_host_dir_rd.57139822825203512336170359921923503505387301370499632314154398956280888733968
Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_host_dir_rd/latest/run.log
... and 3 more failures.
Test default has 1 failures.
Test cover_reg_top has 1 failures.