FLASH_CTRL Simulation Results

Wednesday February 07 2024 20:02:46 UTC

GitHub Revision: `5c87d18988`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 42540109002295994234923032062842839138270099951232798724643629525632267455156

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.716m	39.050us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.510s	59.544us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.030s	43.154us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.470s	102.942us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.384m	9.523ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.249m	8.024ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	18.210s	169.603us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.470s	102.942us	20	20	100.00
		flash_ctrl_csr_aliasing	1.249m	8.024ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.330s	28.899us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.510s	53.553us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.860s	24.357us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.531m	50.912us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	31.370m	129.854ms	3	3	100.00
		flash_ctrl_hw_rma_reset	16.274m	230.219ms	13	20	65.00
		flash_ctrl_lcmgr_intg	14.350s	15.555us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	42.114m	246.474ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	9.415m	18.627ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	1.135m	740.554us	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	55.301m	489.666ms	2	5	40.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	4.201m	13.365ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	37.090s	147.623us	29	40	72.50
		flash_ctrl_rw_evict_all_en	32.700s	37.779us	33	40	82.50
		flash_ctrl_re_evict	41.100s	143.934us	14	20	70.00
V2	host_arb	flash_ctrl_phy_arb	9.646m	2.143ms	19	20	95.00
V2	host_interleave	flash_ctrl_phy_arb	9.646m	2.143ms	19	20	95.00
V2	memory_protection	flash_ctrl_mp_regions	19.013m	160.442ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	27.740s	548.138us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	23.286m	5.590ms	19	20	95.00
V2	error_mp	flash_ctrl_error_mp	42.883m	27.736ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	17.783m	1.151ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	43.975m	503.642us	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.110s	15.038us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.406m	6.305ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	23.380s	20.131us	20	50	40.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.560s	15.723us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	15.679m	1.713ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	3.557m	5.210ms	50	50	100.00
		flash_ctrl_otp_reset	2.255m	143.533us	36	80	45.00
V2	isolation_partition	flash_ctrl_hw_rma	31.370m	129.854ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	3.021m	2.992ms	39	40	97.50
		flash_ctrl_intr_wr	2.115m	58.475ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	5.376m	175.098ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	7.843m	172.380ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.540m	1.018ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.299m	12.851ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.110s	13.734us	3	5	60.00
		flash_ctrl_ro_derr	2.263m	2.034ms	0	10	0.00
		flash_ctrl_rw_derr	9.453m	5.512ms	0	10	0.00
		flash_ctrl_derr_detect	1.799m	368.322us	5	5	100.00
		flash_ctrl_integrity	10.084m	16.833ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.030s	23.994us	5	5	100.00
		flash_ctrl_ro_serr	2.359m	722.372us	10	10	100.00
		flash_ctrl_rw_serr	11.470m	4.026ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.208m	12.271ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	59.420s	1.867ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.686m	10.337ms	20	20	100.00
		flash_ctrl_write_word_sweep	16.720s	61.532us	1	1	100.00
		flash_ctrl_read_word_sweep	14.520s	58.087us	1	1	100.00
		flash_ctrl_ro	2.103m	424.006us	20	20	100.00
		flash_ctrl_rw	9.993m	66.499ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	38.070s	306.970us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	16.164m	61.291ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	2.472m	10.019ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	16.230s	474.672us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.810s	28.509us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	19.580s	220.473us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	19.580s	220.473us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.030s	43.154us	5	5	100.00
		flash_ctrl_csr_rw	17.470s	102.942us	20	20	100.00
		flash_ctrl_csr_aliasing	1.249m	8.024ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.880s	868.680us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.030s	43.154us	5	5	100.00
		flash_ctrl_csr_rw	17.470s	102.942us	20	20	100.00
		flash_ctrl_csr_aliasing	1.249m	8.024ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.880s	868.680us	20	20	100.00
V2		TOTAL			880	1013	86.87
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	15.860s	13.070us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	15.860s	13.070us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	15.860s	13.070us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	15.860s	13.070us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.190s	21.839us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.329h	1.280ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.277m	363.241us	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.277m	363.241us	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.277m	363.241us	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	31.830s	209.733us	2	3	66.67
		flash_ctrl_wr_intg	15.190s	677.334us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.716m	39.050us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.255m	143.533us	36	80	45.00
		flash_ctrl_disable	23.380s	20.131us	20	50	40.00
		flash_ctrl_sec_info_access	1.358m	2.398ms	50	50	100.00
		flash_ctrl_connect	16.560s	15.723us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.010s	171.692us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.470s	102.942us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.860s	13.070us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.470s	102.942us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.860s	13.070us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.470s	102.942us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	15.860s	13.070us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	23.380s	20.131us	20	50	40.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	31.830s	209.733us	2	3	66.67
		flash_ctrl_access_after_disable	13.570s	22.835us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	23.380s	20.131us	20	50	40.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	27.740s	548.138us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	9.993m	66.499ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	11.470m	4.026ms	10	10	100.00
		flash_ctrl_rw_derr	9.453m	5.512ms	0	10	0.00
		flash_ctrl_integrity	10.084m	16.833ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	31.370m	129.854ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.329h	1.280ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.329h	1.280ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.329h	1.280ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.329h	1.280ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	21.100s	105.356us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.340s	15.361us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.090s	27.081us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.329h	1.280ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.329h	1.280ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.329h	1.280ms	5	5	100.00
V2S		TOTAL			143	144	99.31
V3	asymmetric_read_path	flash_ctrl_rd_ooo	43.890s	84.542us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1144	1278	89.51

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	42	76.36
V2S	12	12	11	91.67
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.01	95.34	93.95	98.95	90.48	97.21	98.31	97.84

Failure Buckets

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'val' while register 'flash_ctrl_core_reg_block.dis' is being accessed has 81 failures:

Test flash_ctrl_otp_reset has 44 failures.

0.flash_ctrl_otp_reset.20027942243358827773301430764472589857568951662860523922091873532192719923743
Line 288, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_otp_reset/latest/run.log

  UVM_WARNING @ 6032.9 ns: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'val' while register 'flash_ctrl_core_reg_block.dis' is being accessed
  UVM_INFO @ 6252.9 ns: (flash_ctrl_otp_reset_vseq.sv:130) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.flash_ctrl_otp_reset_vseq] RESET
  UVM_INFO @ 7872.9 ns: (mem_bkdr_util.sv:529) [mem_bkdr_util[FlashPartData][0]] Set memory
  UVM_INFO @ 7872.9 ns: (mem_bkdr_util.sv:529) [mem_bkdr_util[FlashPartData][1]] Set memory
  UVM_INFO @ 7872.9 ns: (mem_bkdr_util.sv:529) [mem_bkdr_util[FlashPartInfo][0]] Set memory

4.flash_ctrl_otp_reset.63391324874043274112092177071275461872651992937720438941562305775942416663904
Line 377, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_otp_reset/latest/run.log

  UVM_WARNING @ 133915.1 ns: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'val' while register 'flash_ctrl_core_reg_block.dis' is being accessed
  UVM_INFO @ 134603.7 ns: (flash_ctrl_otp_reset_vseq.sv:130) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.flash_ctrl_otp_reset_vseq] RESET
  UVM_INFO @ 137921.5 ns: (flash_mem_bkdr_util.sv:26) [mem_bkdr_util[FlashPartData][0]] Randomizing flash mem contents
  UVM_INFO @ 137921.5 ns: (flash_mem_bkdr_util.sv:26) [mem_bkdr_util[FlashPartData][1]] Randomizing flash mem contents
  UVM_INFO @ 137921.5 ns: (flash_mem_bkdr_util.sv:26) [mem_bkdr_util[FlashPartInfo][0]] Randomizing flash mem contents

... and 42 more failures.

Test flash_ctrl_disable has 30 failures.

1.flash_ctrl_disable.32261424514598530418348039006438171985902124634409512957196735022186240523190
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_disable/latest/run.log

  UVM_WARNING @ 29497.1 ns: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'val' while register 'flash_ctrl_core_reg_block.dis' is being accessed
  UVM_INFO @ 35703.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.flash_ctrl_disable.23227629841324894968875908625726775644517486496089396573266404701041535248085
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_disable/latest/run.log

  UVM_WARNING @ 5223.3 ns: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'val' while register 'flash_ctrl_core_reg_block.dis' is being accessed
  UVM_INFO @ 11153.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 28 more failures.

Test flash_ctrl_hw_rma_reset has 7 failures.

2.flash_ctrl_hw_rma_reset.55260717656620109670927666882639397320055514195465308744165334753092012844259
Line 291, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_hw_rma_reset/latest/run.log

  UVM_WARNING @ 18346.1 ns: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'val' while register 'flash_ctrl_core_reg_block.dis' is being accessed
  UVM_INFO @ 18574.9 ns: (flash_ctrl_hw_rma_reset_vseq.sv:72) uvm_test_top.env.virtual_sequencer [Test] RESET
  UVM_INFO @ 20259.7 ns: (flash_mem_bkdr_util.sv:26) [mem_bkdr_util[FlashPartData][0]] Randomizing flash mem contents
  UVM_INFO @ 20259.7 ns: (flash_mem_bkdr_util.sv:26) [mem_bkdr_util[FlashPartData][1]] Randomizing flash mem contents
  UVM_INFO @ 20259.7 ns: (flash_mem_bkdr_util.sv:26) [mem_bkdr_util[FlashPartInfo][0]] Randomizing flash mem contents

3.flash_ctrl_hw_rma_reset.40221976424130402168553051846330455287305164051977608746933601240433255267287
Line 291, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_hw_rma_reset/latest/run.log

  UVM_WARNING @ 9032.5 ns: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'val' while register 'flash_ctrl_core_reg_block.dis' is being accessed
  UVM_INFO @ 9144.7 ns: (flash_ctrl_hw_rma_reset_vseq.sv:72) uvm_test_top.env.virtual_sequencer [Test] RESET
  UVM_INFO @ 10021.9 ns: (mem_bkdr_util.sv:529) [mem_bkdr_util[FlashPartData][0]] Set memory
  UVM_INFO @ 10021.9 ns: (mem_bkdr_util.sv:529) [mem_bkdr_util[FlashPartData][1]] Set memory
  UVM_INFO @ 10021.9 ns: (mem_bkdr_util.sv:529) [mem_bkdr_util[FlashPartInfo][0]] Set memory

... and 5 more failures.

Offending '(prv_rd_addr != addr)' has 51 failures:
- Test flash_ctrl_read_word_sweep_derr has 2 failures.
  - 0.flash_ctrl_read_word_sweep_derr.17131757837767991608182268798613140092737934025360792119137526426019046640880
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep_derr/latest/run.log
```
      Offending '(prv_rd_addr != addr)'
  UVM_ERROR @ 12900.3 ns: (flash_ctrl_phy_cov_if.sv:76) [ASSERT FAILED] NoSameAddrRead_A
  UVM_INFO @ 12900.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 3.flash_ctrl_read_word_sweep_derr.76633564394470038656074616592296194210369965027576604696168616853188664528228
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_derr/latest/run.log
```
      Offending '(prv_rd_addr != addr)'
  UVM_ERROR @ 13734.0 ns: (flash_ctrl_phy_cov_if.sv:76) [ASSERT FAILED] NoSameAddrRead_A
  UVM_INFO @ 13734.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_ro_derr has 10 failures.
  - 0.flash_ctrl_ro_derr.43687095559737056319800840902641401336419389293645059864303400208755461816742
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_ro_derr/latest/run.log
```
      Offending '(prv_rd_addr != addr)'
  UVM_ERROR @ 499661.5 ns: (flash_ctrl_phy_cov_if.sv:76) [ASSERT FAILED] NoSameAddrRead_A
  UVM_INFO @ 499661.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.flash_ctrl_ro_derr.103761418655560598542955434247749907658883622974456450840382241794120520826118
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_ro_derr/latest/run.log
```
      Offending '(prv_rd_addr != addr)'
  UVM_ERROR @ 473151.0 ns: (flash_ctrl_phy_cov_if.sv:76) [ASSERT FAILED] NoSameAddrRead_A
  UVM_INFO @ 473151.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 8 more failures.
- Test flash_ctrl_rw_derr has 10 failures.
  - 0.flash_ctrl_rw_derr.112096272035064106270950148311231562522531492234096664565031442606630518475210
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_derr/latest/run.log
```
      Offending '(prv_rd_addr != addr)'
  UVM_ERROR @ 5512459.8 ns: (flash_ctrl_phy_cov_if.sv:76) [ASSERT FAILED] NoSameAddrRead_A
  UVM_INFO @ 5512459.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.flash_ctrl_rw_derr.72456741696908271504773442627799089259719418730273760288834619399133915265608
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest/run.log
```
      Offending '(prv_rd_addr != addr)'
  UVM_ERROR @ 17395862.1 ns: (flash_ctrl_phy_cov_if.sv:76) [ASSERT FAILED] NoSameAddrRead_A
  UVM_INFO @ 17395862.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 8 more failures.
- Test flash_ctrl_rw_evict has 10 failures.
  - 1.flash_ctrl_rw_evict.24553046071567322030550806677884545932166399287585865103622236239809903166174
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict/latest/run.log
```
      Offending '(prv_rd_addr != addr)'
  UVM_ERROR @ 60104.6 ns: (flash_ctrl_phy_cov_if.sv:76) [ASSERT FAILED] NoSameAddrRead_A
  UVM_INFO @ 60104.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 9.flash_ctrl_rw_evict.112886781925554382861939665710317840161938735370579025822117269485925694038305
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_rw_evict/latest/run.log
```
      Offending '(prv_rd_addr != addr)'
  UVM_ERROR @ 62915.0 ns: (flash_ctrl_phy_cov_if.sv:76) [ASSERT FAILED] NoSameAddrRead_A
  UVM_INFO @ 62915.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 8 more failures.
- Test flash_ctrl_re_evict has 6 failures.
  - 1.flash_ctrl_re_evict.15299973872825461393871676789647411632754924371080120418243963184509487285603
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_re_evict/latest/run.log
```
      Offending '(prv_rd_addr != addr)'
  UVM_ERROR @ 170041.3 ns: (flash_ctrl_phy_cov_if.sv:76) [ASSERT FAILED] NoSameAddrRead_A
  UVM_INFO @ 170041.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 2.flash_ctrl_re_evict.16864910524287277845548412238715354838553437659688051824810043446233515296619
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_re_evict/latest/run.log
```
      Offending '(prv_rd_addr != addr)'
  UVM_ERROR @ 71857.3 ns: (flash_ctrl_phy_cov_if.sv:76) [ASSERT FAILED] NoSameAddrRead_A
  UVM_INFO @ 71857.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 4 more failures.
- ... and 6 more tests.
Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test flash_ctrl_full_mem_access has 1 failures.
  - 1.flash_ctrl_full_mem_access.29205651646814990802262119966290626000722549214677482971374469004433657797953
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_full_mem_access/latest/run.log
```
  Job ID: smart:8b0b6e9f-285f-4c50-902f-07b0fba37fdb
```
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 7.flash_ctrl_rw_evict.103702601917991066100400500898581555265840336244304580796256971340093060295551
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 50197.5 ns: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 50197.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```