FLASH_CTRL Simulation Results

Sunday February 04 2024 20:02:57 UTC

GitHub Revision: `0dd29ab736`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 76373007482531906509957308269646114477602578576554530782790132514100107307713

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.218m	79.214us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.380s	56.870us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	44.370s	90.450us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.220s	255.939us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.451m	36.418ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	59.590s	1.583ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	18.620s	80.570us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.220s	255.939us	20	20	100.00
		flash_ctrl_csr_aliasing	59.590s	1.583ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.450s	16.941us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.670s	16.316us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.350s	23.228us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.669m	58.349us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	34.453m	134.713ms	3	3	100.00
		flash_ctrl_hw_rma_reset	26.060m	760.463ms	9	20	45.00
		flash_ctrl_lcmgr_intg	14.010s	47.072us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	43.933m	271.003ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	9.077m	15.204ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.941m	10.775ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	42.015m	93.162ms	3	5	60.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.455m	789.609us	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	35.600s	112.068us	39	40	97.50
		flash_ctrl_rw_evict_all_en	37.730s	124.330us	40	40	100.00
		flash_ctrl_re_evict	40.350s	701.818us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	7.825m	737.731us	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	7.825m	737.731us	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	19.810m	133.605ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	32.180s	7.473ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	21.330m	8.626ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	40.001m	19.323ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	23.659m	1.055ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	45.232m	2.031ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.110s	44.860us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.490m	2.555ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.760s	20.852us	28	50	56.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.040s	45.554us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	14.617m	3.249ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.314m	6.506ms	50	50	100.00
		flash_ctrl_otp_reset	2.240m	44.318us	40	80	50.00
V2	isolation_partition	flash_ctrl_hw_rma	34.453m	134.713ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	3.280m	4.213ms	40	40	100.00
		flash_ctrl_intr_wr	2.165m	19.935ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	5.192m	162.335ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	8.716m	200.731ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.628m	1.953ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.221m	4.581ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.570s	19.118us	5	5	100.00
		flash_ctrl_ro_derr	2.833m	1.430ms	10	10	100.00
		flash_ctrl_rw_derr	13.491m	9.135ms	10	10	100.00
		flash_ctrl_derr_detect	1.758m	202.651us	5	5	100.00
		flash_ctrl_integrity	11.239m	4.529ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.350s	35.245us	5	5	100.00
		flash_ctrl_ro_serr	2.561m	1.338ms	10	10	100.00
		flash_ctrl_rw_serr	10.595m	12.898ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	59.600s	1.735ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.868m	4.391ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.710m	2.615ms	20	20	100.00
		flash_ctrl_write_word_sweep	17.140s	128.892us	1	1	100.00
		flash_ctrl_read_word_sweep	14.360s	41.596us	1	1	100.00
		flash_ctrl_ro	2.032m	462.872us	20	20	100.00
		flash_ctrl_rw	11.520m	8.985ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	36.300s	359.709us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	20.774m	90.458ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	4.870m	10.013ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	17.800s	858.099us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.220s	55.853us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	19.350s	67.803us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	19.350s	67.803us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	44.370s	90.450us	5	5	100.00
		flash_ctrl_csr_rw	17.220s	255.939us	20	20	100.00
		flash_ctrl_csr_aliasing	59.590s	1.583ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.520s	203.815us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	44.370s	90.450us	5	5	100.00
		flash_ctrl_csr_rw	17.220s	255.939us	20	20	100.00
		flash_ctrl_csr_aliasing	59.590s	1.583ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.520s	203.815us	20	20	100.00
V2		TOTAL			937	1013	92.50
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	15.650s	22.445us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	15.650s	22.445us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	15.650s	22.445us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	15.650s	22.445us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	15.670s	21.133us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.325h	3.774ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.228m	10.976ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.228m	10.976ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.228m	10.976ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	31.760s	269.000us	3	3	100.00
		flash_ctrl_wr_intg	14.700s	89.368us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.218m	79.214us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.240m	44.318us	40	80	50.00
		flash_ctrl_disable	22.760s	20.852us	28	50	56.00
		flash_ctrl_sec_info_access	1.800m	18.872ms	50	50	100.00
		flash_ctrl_connect	16.040s	45.554us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.060s	88.797us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.220s	255.939us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.650s	22.445us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.220s	255.939us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.650s	22.445us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.220s	255.939us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	15.650s	22.445us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.760s	20.852us	28	50	56.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	31.760s	269.000us	3	3	100.00
		flash_ctrl_access_after_disable	13.740s	40.844us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.760s	20.852us	28	50	56.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	32.180s	7.473ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.520m	8.985ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	10.595m	12.898ms	10	10	100.00
		flash_ctrl_rw_derr	13.491m	9.135ms	10	10	100.00
		flash_ctrl_integrity	11.239m	4.529ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	34.453m	134.713ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.325h	3.774ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.325h	3.774ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.325h	3.774ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.325h	3.774ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	19.550s	115.163us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	13.980s	44.537us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.420s	31.241us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.325h	3.774ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.325h	3.774ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.325h	3.774ms	5	5	100.00
V2S		TOTAL			144	144	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	42.920s	79.305us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1202	1278	94.05

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	50	90.91
V2S	12	12	12	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.35	95.87	94.18	98.95	90.48	98.46	98.30	98.19

Failure Buckets

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'val' while register 'flash_ctrl_core_reg_block.dis' is being accessed has 73 failures:

Test flash_ctrl_hw_rma_reset has 11 failures.

0.flash_ctrl_hw_rma_reset.40349911707105279319369953525216265731660957553810943877981103405501702411509
Line 291, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_hw_rma_reset/latest/run.log

  UVM_WARNING @ 7348.6 ns: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'val' while register 'flash_ctrl_core_reg_block.dis' is being accessed
  UVM_INFO @ 7460.8 ns: (flash_ctrl_hw_rma_reset_vseq.sv:72) uvm_test_top.env.virtual_sequencer [Test] RESET
  UVM_INFO @ 8256.4 ns: (flash_mem_bkdr_util.sv:26) [mem_bkdr_util[FlashPartData][0]] Randomizing flash mem contents
  UVM_INFO @ 8256.4 ns: (flash_mem_bkdr_util.sv:26) [mem_bkdr_util[FlashPartData][1]] Randomizing flash mem contents
  UVM_INFO @ 8256.4 ns: (flash_mem_bkdr_util.sv:26) [mem_bkdr_util[FlashPartInfo][0]] Randomizing flash mem contents

2.flash_ctrl_hw_rma_reset.17606713885068677587017488658581907772891283803645149932227616711694676173627
Line 291, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_hw_rma_reset/latest/run.log

  UVM_WARNING @ 31015.0 ns: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'val' while register 'flash_ctrl_core_reg_block.dis' is being accessed
  UVM_INFO @ 31382.4 ns: (flash_ctrl_hw_rma_reset_vseq.sv:72) uvm_test_top.env.virtual_sequencer [Test] RESET
  UVM_INFO @ 33119.2 ns: (flash_mem_bkdr_util.sv:26) [mem_bkdr_util[FlashPartData][0]] Randomizing flash mem contents
  UVM_INFO @ 33119.2 ns: (flash_mem_bkdr_util.sv:26) [mem_bkdr_util[FlashPartData][1]] Randomizing flash mem contents
  UVM_INFO @ 33119.2 ns: (flash_mem_bkdr_util.sv:26) [mem_bkdr_util[FlashPartInfo][0]] Randomizing flash mem contents

... and 9 more failures.

Test flash_ctrl_otp_reset has 40 failures.

1.flash_ctrl_otp_reset.69453508157144656416935647703500899512775411011242731045683189036182018436101
Line 387, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_otp_reset/latest/run.log

  UVM_WARNING @ 50642.7 ns: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'val' while register 'flash_ctrl_core_reg_block.dis' is being accessed
  UVM_INFO @ 50867.1 ns: (flash_ctrl_otp_reset_vseq.sv:130) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.flash_ctrl_otp_reset_vseq] RESET
  UVM_INFO @ 52499.1 ns: (flash_mem_bkdr_util.sv:26) [mem_bkdr_util[FlashPartData][0]] Randomizing flash mem contents
  UVM_INFO @ 52499.1 ns: (flash_mem_bkdr_util.sv:26) [mem_bkdr_util[FlashPartData][1]] Randomizing flash mem contents
  UVM_INFO @ 52499.1 ns: (flash_mem_bkdr_util.sv:26) [mem_bkdr_util[FlashPartInfo][0]] Randomizing flash mem contents

6.flash_ctrl_otp_reset.16793351976204498052089394751819064675623299492115190272511658030656832842577
Line 288, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_otp_reset/latest/run.log

  UVM_WARNING @ 6426.3 ns: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'val' while register 'flash_ctrl_core_reg_block.dis' is being accessed
  UVM_INFO @ 6716.7 ns: (flash_ctrl_otp_reset_vseq.sv:130) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.flash_ctrl_otp_reset_vseq] RESET
  UVM_INFO @ 8907.9 ns: (flash_mem_bkdr_util.sv:26) [mem_bkdr_util[FlashPartData][0]] Randomizing flash mem contents
  UVM_INFO @ 8907.9 ns: (flash_mem_bkdr_util.sv:26) [mem_bkdr_util[FlashPartData][1]] Randomizing flash mem contents
  UVM_INFO @ 8907.9 ns: (flash_mem_bkdr_util.sv:26) [mem_bkdr_util[FlashPartInfo][0]] Randomizing flash mem contents

... and 38 more failures.

Test flash_ctrl_disable has 22 failures.

2.flash_ctrl_disable.112097797425706617573298749180697076454991869024634259547112161379540382753410
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_disable/latest/run.log

  UVM_WARNING @ 4785.2 ns: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'val' while register 'flash_ctrl_core_reg_block.dis' is being accessed
  UVM_INFO @ 10195.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.flash_ctrl_disable.67850424499754875807167801125559741447046707324658644904348387562763981731351
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_disable/latest/run.log

  UVM_WARNING @ 12572.6 ns: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'val' while register 'flash_ctrl_core_reg_block.dis' is being accessed
  UVM_INFO @ 18259.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 20 more failures.

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test flash_ctrl_full_mem_access has 2 failures.
  - 0.flash_ctrl_full_mem_access.68491946306368983135339287512607963738289610468507009319678156912367606470997
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_full_mem_access/latest/run.log
```
  Job ID: smart:d0ea8d8a-8880-4ef1-86bb-1ebd2bb55534
```
  - 2.flash_ctrl_full_mem_access.95587835855294952642099282618186903001358087435555768433332390390065913009351
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_full_mem_access/latest/run.log
```
  Job ID: smart:2990e5e2-109f-4573-a698-6bca5ba5168b
```
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 15.flash_ctrl_rw_evict.68967583321373997364803124093918812382805306411113050085198840511263099602159
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 14724.1 ns: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 14724.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```