FLASH_CTRL Simulation Results

Wednesday January 24 2024 20:02:24 UTC

GitHub Revision: `17d5a97c3b`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 111545506019531132515166311410934274348263845011639206515682989027305484635840

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.373m	735.837us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.820s	57.911us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	47.060s	44.681us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.690s	71.953us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.329m	4.561ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	38.080s	891.801us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.220s	43.581us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.690s	71.953us	20	20	100.00
		flash_ctrl_csr_aliasing	38.080s	891.801us	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.330s	122.299us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.580s	20.638us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.830s	161.097us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.555m	54.623us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	32.911m	128.597ms	3	3	100.00
		flash_ctrl_hw_rma_reset	17.049m	210.209ms	12	20	60.00
		flash_ctrl_lcmgr_intg	14.120s	25.079us	18	20	90.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	40.498m	245.356ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	10.790m	25.059ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	5.600m	30.624ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	40.821m	78.255ms	3	5	60.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.430m	736.130us	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	40.610s	641.326us	40	40	100.00
		flash_ctrl_rw_evict_all_en	37.910s	153.171us	40	40	100.00
		flash_ctrl_re_evict	42.590s	148.440us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	10.531m	3.802ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	10.531m	3.802ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	17.520m	51.215ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	31.330s	8.051ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	26.379m	2.294ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	42.363m	15.647ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	17.823m	2.019ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	49.590m	1.341ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.300s	57.950us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.388m	17.856ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	3.613m	10.028ms	32	50	64.00
V2	flash_ctrl_connect	flash_ctrl_connect	17.400s	21.462us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	28.031m	2.044ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.120m	15.767ms	50	50	100.00
		flash_ctrl_otp_reset	2.352m	152.388us	32	80	40.00
V2	isolation_partition	flash_ctrl_hw_rma	32.911m	128.597ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	3.265m	4.808ms	40	40	100.00
		flash_ctrl_intr_wr	2.512m	36.678ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	5.378m	105.649ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	18.762m	950.820ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.501m	1.017ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.344m	994.093us	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.000s	33.591us	5	5	100.00
		flash_ctrl_ro_derr	2.836m	654.381us	10	10	100.00
		flash_ctrl_rw_derr	11.659m	4.090ms	10	10	100.00
		flash_ctrl_derr_detect	1.772m	201.183us	5	5	100.00
		flash_ctrl_integrity	10.596m	4.408ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.590s	78.857us	5	5	100.00
		flash_ctrl_ro_serr	2.782m	644.037us	10	10	100.00
		flash_ctrl_rw_serr	11.585m	11.828ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.312m	1.338ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.246m	10.683ms	5	5	100.00
V2	scramble	flash_ctrl_wo	4.066m	8.302ms	20	20	100.00
		flash_ctrl_write_word_sweep	17.550s	61.888us	1	1	100.00
		flash_ctrl_read_word_sweep	13.490s	18.689us	1	1	100.00
		flash_ctrl_ro	2.103m	872.401us	20	20	100.00
		flash_ctrl_rw	10.973m	15.893ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	38.350s	5.178ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	14.611m	40.745ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	3.780m	10.015ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.520s	78.992us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.780s	59.963us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.180s	226.813us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.180s	226.813us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	47.060s	44.681us	5	5	100.00
		flash_ctrl_csr_rw	17.690s	71.953us	20	20	100.00
		flash_ctrl_csr_aliasing	38.080s	891.801us	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.340s	777.599us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	47.060s	44.681us	5	5	100.00
		flash_ctrl_csr_rw	17.690s	71.953us	20	20	100.00
		flash_ctrl_csr_aliasing	38.080s	891.801us	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.340s	777.599us	20	20	100.00
V2		TOTAL			935	1013	92.30
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.030s	17.803us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.030s	17.803us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.030s	17.803us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.030s	17.803us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.490s	17.092us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.363h	13.821ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.233m	3.332ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.233m	3.332ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.233m	3.332ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.880s	114.770us	3	3	100.00
		flash_ctrl_wr_intg	15.050s	42.591us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.373m	735.837us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.352m	152.388us	32	80	40.00
		flash_ctrl_disable	3.613m	10.028ms	32	50	64.00
		flash_ctrl_sec_info_access	1.463m	4.675ms	50	50	100.00
		flash_ctrl_connect	17.400s	21.462us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.320s	47.154us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.690s	71.953us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.030s	17.803us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.690s	71.953us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.030s	17.803us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.690s	71.953us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.030s	17.803us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	3.613m	10.028ms	32	50	64.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.880s	114.770us	3	3	100.00
		flash_ctrl_access_after_disable	14.200s	14.357us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	3.613m	10.028ms	32	50	64.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	31.330s	8.051ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	10.973m	15.893ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	11.585m	11.828ms	10	10	100.00
		flash_ctrl_rw_derr	11.659m	4.090ms	10	10	100.00
		flash_ctrl_integrity	10.596m	4.408ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	32.911m	128.597ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.363h	13.821ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.363h	13.821ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.363h	13.821ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.363h	13.821ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	18.740s	85.452us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.200s	110.424us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	20.110s	366.112us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.363h	13.821ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.363h	13.821ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.363h	13.821ms	5	5	100.00
V2S		TOTAL			144	144	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	45.490s	99.462us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1200	1278	93.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	50	90.91
V2S	12	12	12	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.23	95.87	93.99	97.91	90.48	98.40	98.62	98.36

Failure Buckets

UVM_WARNING (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'val' while register 'flash_ctrl_core_reg_block.dis' is being accessed has 73 failures:

Test flash_ctrl_otp_reset has 47 failures.

0.flash_ctrl_otp_reset.6559362459604574188597679574552803738324910829169880609325436993817748955469
Line 316, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_otp_reset/latest/run.log

  UVM_WARNING @ 9252.7 ns: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'val' while register 'flash_ctrl_core_reg_block.dis' is being accessed
  UVM_INFO @ 9483.1 ns: (flash_ctrl_otp_reset_vseq.sv:130) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.flash_ctrl_otp_reset_vseq] RESET
  UVM_INFO @ 10135.9 ns: (flash_mem_bkdr_util.sv:26) [mem_bkdr_util[FlashPartData][0]] Randomizing flash mem contents
  UVM_INFO @ 10135.9 ns: (flash_mem_bkdr_util.sv:26) [mem_bkdr_util[FlashPartData][1]] Randomizing flash mem contents
  UVM_INFO @ 10135.9 ns: (flash_mem_bkdr_util.sv:26) [mem_bkdr_util[FlashPartInfo][0]] Randomizing flash mem contents

2.flash_ctrl_otp_reset.21093457948393327873108413929378242587897224874883306118539525168669466363167
Line 344, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_otp_reset/latest/run.log

  UVM_WARNING @ 20152.5 ns: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'val' while register 'flash_ctrl_core_reg_block.dis' is being accessed
  UVM_INFO @ 20303.2 ns: (flash_ctrl_otp_reset_vseq.sv:130) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.flash_ctrl_otp_reset_vseq] RESET
  UVM_INFO @ 21399.2 ns: (flash_mem_bkdr_util.sv:26) [mem_bkdr_util[FlashPartData][0]] Randomizing flash mem contents
  UVM_INFO @ 21399.2 ns: (flash_mem_bkdr_util.sv:26) [mem_bkdr_util[FlashPartData][1]] Randomizing flash mem contents
  UVM_INFO @ 21399.2 ns: (flash_mem_bkdr_util.sv:26) [mem_bkdr_util[FlashPartInfo][0]] Randomizing flash mem contents

... and 45 more failures.

Test flash_ctrl_hw_rma_reset has 8 failures.

4.flash_ctrl_hw_rma_reset.22154719808458609959906096664768133440501019250004456335425565150844681275789
Line 291, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_hw_rma_reset/latest/run.log

  UVM_WARNING @ 19339.8 ns: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'val' while register 'flash_ctrl_core_reg_block.dis' is being accessed
  UVM_INFO @ 19686.6 ns: (flash_ctrl_hw_rma_reset_vseq.sv:72) uvm_test_top.env.virtual_sequencer [Test] RESET
  UVM_INFO @ 21012.6 ns: (mem_bkdr_util.sv:529) [mem_bkdr_util[FlashPartData][0]] Set memory
  UVM_INFO @ 21012.6 ns: (mem_bkdr_util.sv:529) [mem_bkdr_util[FlashPartData][1]] Set memory
  UVM_INFO @ 21012.6 ns: (mem_bkdr_util.sv:529) [mem_bkdr_util[FlashPartInfo][0]] Set memory

5.flash_ctrl_hw_rma_reset.58467555495439462452209873362349220435375846499316258707339250636093477989673
Line 291, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_hw_rma_reset/latest/run.log

  UVM_WARNING @ 27992.4 ns: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'val' while register 'flash_ctrl_core_reg_block.dis' is being accessed
  UVM_INFO @ 28414.8 ns: (flash_ctrl_hw_rma_reset_vseq.sv:72) uvm_test_top.env.virtual_sequencer [Test] RESET
  UVM_INFO @ 31755.6 ns: (flash_mem_bkdr_util.sv:26) [mem_bkdr_util[FlashPartData][0]] Randomizing flash mem contents
  UVM_INFO @ 31755.6 ns: (flash_mem_bkdr_util.sv:26) [mem_bkdr_util[FlashPartData][1]] Randomizing flash mem contents
  UVM_INFO @ 31755.6 ns: (flash_mem_bkdr_util.sv:26) [mem_bkdr_util[FlashPartInfo][0]] Randomizing flash mem contents

... and 6 more failures.

Test flash_ctrl_disable has 18 failures.

8.flash_ctrl_disable.18962792876690216114926982409907158601227565195133437121006036404346364560980
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_disable/latest/run.log

  UVM_WARNING @ 27576.8 ns: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'val' while register 'flash_ctrl_core_reg_block.dis' is being accessed
  UVM_FATAL @ 10028152.8 ns: (csr_utils_pkg.sv:566) [csr_utils::csr_spinwait] timeout flash_ctrl_core_reg_block.status.rd_empty (addr=0x95043374) == 0x1
  UVM_INFO @ 10028152.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.flash_ctrl_disable.19431149349872986302159245486459166374434589227274552362028663165741463333317
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_disable/latest/run.log

  UVM_WARNING @ 60686.6 ns: (uvm_reg_field.svh:1191) [RegModel] Trying to predict value of field 'val' while register 'flash_ctrl_core_reg_block.dis' is being accessed
  UVM_INFO @ 87785.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 16 more failures.

Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test flash_ctrl_full_mem_access has 2 failures.
  - 1.flash_ctrl_full_mem_access.68016119327677761862990880461309310368226559632842156389642063576665793084634
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_full_mem_access/latest/run.log
```
  Job ID: smart:6d899a37-d153-4903-ae9b-31cdf6f42d86
```
  - 4.flash_ctrl_full_mem_access.19303212963305733308321146406149149963882692967765681810601757545709028289153
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_full_mem_access/latest/run.log
```
  Job ID: smart:f2bb15bd-edff-4bf3-82a5-f30a0722904e
```
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.std_fault_status.lcmgr_intg_err reset value: * has 2 failures:
- Test flash_ctrl_lcmgr_intg has 2 failures.
  - 5.flash_ctrl_lcmgr_intg.19720350776111443292688668791876787184583721059511285566222407450881800133775
    Line 285, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_lcmgr_intg/latest/run.log
```
  UVM_ERROR @ 6573.7 ns: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.std_fault_status.lcmgr_intg_err reset value: 0x0
  UVM_INFO @ 6573.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 19.flash_ctrl_lcmgr_intg.64128263757523266255764813904640770173908562332535966186954650499918061526074
    Line 285, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_lcmgr_intg/latest/run.log
```
  UVM_ERROR @ 7840.4 ns: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.std_fault_status.lcmgr_intg_err reset value: 0x0
  UVM_INFO @ 7840.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending 'dst_req_o' has 1 failures:
- Test flash_ctrl_otp_reset has 1 failures.
  - 1.flash_ctrl_otp_reset.74156816272169975533106590009112965737391523617597878326938246559893121418791
    Line 354, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_otp_reset/latest/run.log
```
      Offending 'dst_req_o'
  UVM_ERROR @ 15636.7 ns: (prim_sync_reqack.sv:354) [ASSERT FAILED] SyncReqAckAckNeedsReq
  UVM_INFO @ 15636.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```