Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	97.92	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	95.83	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	23925	1		T11	858		T4	8		T12	1054
full_word	8096	1		T11	253		T4	1		T12	299

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	31760	1		T11	1111		T12	1353		T14	1436
auto[TlIntgErrCmd]	85	1		T4	4		T5	6		T6	2
auto[TlIntgErrData]	92	1		T4	4		T5	7		T6	2
auto[TlIntgErrBoth]	84	1		T4	1		T5	6		T6	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1871	1		T11	57		T4	1		T12	98
auto[1]	30150	1		T11	1054		T4	8		T12	1255

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER
[auto[TlIntgErrCmd]]	[full_word]	[auto[0]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1553	1		T11	48		T12	83		T14	75
auto[TlIntgErrNone]	partial	auto[1]	22130	1		T11	810		T12	971		T14	996
auto[TlIntgErrNone]	full_word	auto[0]	211	1		T11	9		T12	15		T14	9
auto[TlIntgErrNone]	full_word	auto[1]	7866	1		T11	244		T12	284		T14	356
auto[TlIntgErrCmd]	partial	auto[0]	30	1		T4	1		T5	1		T6	1
auto[TlIntgErrCmd]	partial	auto[1]	53	1		T4	3		T5	4		T6	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1		T5	1		T90	1		-	-
auto[TlIntgErrData]	partial	auto[0]	38	1		T5	2		T6	2		T23	1
auto[TlIntgErrData]	partial	auto[1]	45	1		T4	3		T5	5		T23	2
auto[TlIntgErrData]	full_word	auto[0]	4	1		T23	1		T57	1		T89	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T4	1		T62	1		T70	1
auto[TlIntgErrBoth]	partial	auto[0]	30	1		T5	4		T6	1		T23	2
auto[TlIntgErrBoth]	partial	auto[1]	46	1		T4	1		T5	2		T6	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T23	1		T70	1		T88	2
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T23	2		T62	1		-	-

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	235659	1		T1	89		T2	84		T3	61
full_word	174206	1		T1	53		T2	58		T3	42

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	409585	1		T1	142		T2	142		T3	103
auto[TlIntgErrCmd]	82	1		T4	2		T5	5		T6	1
auto[TlIntgErrData]	111	1		T4	6		T5	9		T6	5
auto[TlIntgErrBoth]	87	1		T4	2		T5	6		T6	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	281939	1		T1	77		T2	77		T3	58
auto[1]	127926	1		T1	65		T2	65		T3	45

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	184597	1		T1	69		T2	65		T3	58
auto[TlIntgErrNone]	partial	auto[1]	50806	1		T1	20		T2	19		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	97221	1		T1	8		T2	12		T13	1
auto[TlIntgErrNone]	full_word	auto[1]	76961	1		T1	45		T2	46		T3	42
auto[TlIntgErrCmd]	partial	auto[0]	26	1		T5	2		T6	1		T23	4
auto[TlIntgErrCmd]	partial	auto[1]	49	1		T4	1		T5	3		T23	4
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T68	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T4	1		T66	2		T70	1
auto[TlIntgErrData]	partial	auto[0]	55	1		T4	3		T5	6		T6	1
auto[TlIntgErrData]	partial	auto[1]	42	1		T4	3		T5	3		T6	4
auto[TlIntgErrData]	full_word	auto[0]	5	1		T23	1		T66	1		T68	1
auto[TlIntgErrData]	full_word	auto[1]	9	1		T23	1		T62	1		T91	1
auto[TlIntgErrBoth]	partial	auto[0]	32	1		T5	1		T6	1		T23	1
auto[TlIntgErrBoth]	partial	auto[1]	52	1		T4	2		T5	5		T6	3
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T91	1		T90	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	1	1		T88	1		-	-		-	-