Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : tlul_err
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_to_prog_fifo.u_err 0.00 0.00 0.00 0.00
tb.dut.u_to_rd_fifo.u_err 0.00 0.00 0.00 0.00
tb.dut.u_tl_adapter_eflash.u_err 0.00 0.00 0.00 0.00
tb.dut.u_reg_core.u_reg_if.u_err 100.00 100.00 100.00 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_err 100.00 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_to_prog_fifo.u_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
0.00 0.00 0.00 0.00 u_to_prog_fifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_to_rd_fifo.u_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
0.00 0.00 0.00 0.00 u_to_rd_fifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_tl_adapter_eflash.u_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
0.00 0.00 0.00 0.00 u_tl_adapter_eflash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_reg_if.u_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.96 100.00 91.84 100.00 100.00 u_reg_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
98.91 100.00 95.65 100.00 100.00 u_reg_if


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : tlul_err
Line No.TotalCoveredPercent
TOTAL2626100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3611100.00
CONT_ASSIGN3911100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN5311100.00
ALWAYS561717100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
32 1 1
36 1 1
39 1 1
42 1 1
53 1 1
56 1 1
57 1 1
58 1 1
60 1 1
61 1 1
63 1 1
64 1 1
65 1 1
69 1 1
71 1 1
73 1 1
77 1 1
78 1 1
79 1 1
89 1 1
90 1 1
91 1 1
95 1 1

Cond Coverage for Module : tlul_err
TotalCoveredPercent
Conditions3535100.00
Logical3535100.00
Non-Logical00
Event00

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT11,T4,T12
010CoveredT11,T12,T14
100CoveredT2,T13,T11 

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------
-1--2-StatusTests
01CoveredT11,T4,T12
10CoveredT2,T13,T11
11CoveredT1,T2,T3 

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------
-1--2--3-StatusTests
000CoveredT11,T4,T12
001CoveredT1,T2,T3
010CoveredT1,T2,T3
100CoveredT1,T2,T3 

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       71
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T11,T4 

 LINE       73
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T11,T4 

 LINE       95
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------
-1--2--3-StatusTests
011CoveredT11,T12,T5
101CoveredT11,T12,T5
110CoveredT11,T4,T12
111CoveredT1,T2,T3 

 LINE       95
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----
-1--2--3-StatusTests
000CoveredT2,T13,T11
001CoveredT1,T2,T3
010CoveredT1,T2,T3
100CoveredT1,T2,T3
Branch Coverage for Module : tlul_err
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 8 8 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	60	if (tl_i.a_valid)
-2-:	61	case (tl_i.a_size)
-3-:	71	(tl_i.a_address[1]) ? 
-4-:	73	(tl_i.a_address[1]) ?

Branches:
-1--2--3--4-StatusTests
1 'h0 - - Covered T1,T2,T3
1 'h1 1 - Covered T2,T11,T4
1 'h1 0 - Covered T1,T2,T3
1 'h1 - 1 Covered T2,T11,T4
1 'h1 - 0 Covered T1,T2,T3
1 'h00000002 - - Covered T1,T2,T3
1 default - - Covered T11,T12,T14
0 - - - Covered T1,T2,T3

Assert Coverage for Module : tlul_err
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
dataWidthOnly32_A 430 430 0 0


dataWidthOnly32_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 430 430 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T4 2 2 0 0
T5 2 2 0 0
T7 2 2 0 0
T9 2 2 0 0
T11 2 2 0 0
T12 2 2 0 0
T13 2 2 0 0

Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_err
Line No.TotalCoveredPercent
TOTAL2600.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN28100.00
CONT_ASSIGN32100.00
CONT_ASSIGN36100.00
CONT_ASSIGN39100.00
CONT_ASSIGN42100.00
CONT_ASSIGN53100.00
ALWAYS561700.00
CONT_ASSIGN95100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 0 1
32 0 1
36 0 1
39 0 1
42 0 1
53 0 1
56 0 1
57 0 1
58 0 1
60 0 1
61 0 1
63 0 1
64 0 1
65 0 1
69 0 1
71 0 1
73 0 1
77 0 1
78 0 1
79 0 1
89 0 1
90 0 1
91 0 1
95 0 1

Cond Coverage for Instance : tb.dut.u_to_prog_fifo.u_err
TotalCoveredPercent
Conditions3500.00
Logical3500.00
Non-Logical00
Event00

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------
-1--2--3-StatusTests
000Not Covered
001Not Covered
010Not Covered
100Not Covered 

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------
-1--2--3-StatusTests
000Not Covered
001Not Covered
010Not Covered
100Not Covered 

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       71
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       73
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       95
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered 

 LINE       95
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----
-1--2--3-StatusTests
000Not Covered
001Not Covered
010Not Covered
100Not Covered
Branch Coverage for Instance : tb.dut.u_to_prog_fifo.u_err
Line No.TotalCoveredPercent
Branches 8 0 0.00
IF 60 8 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	60	if (tl_i.a_valid)
-2-:	61	case (tl_i.a_size)
-3-:	71	(tl_i.a_address[1]) ? 
-4-:	73	(tl_i.a_address[1]) ?

Branches:
-1--2--3--4-StatusTests
1 'h0 - - Not Covered
1 'h1 1 - Not Covered
1 'h1 0 - Not Covered
1 'h1 - 1 Not Covered
1 'h1 - 0 Not Covered
1 'h00000002 - - Not Covered
1 default - - Not Covered
0 - - - Not Covered

Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_err
Line No.TotalCoveredPercent
TOTAL2600.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN28100.00
CONT_ASSIGN32100.00
CONT_ASSIGN36100.00
CONT_ASSIGN39100.00
CONT_ASSIGN42100.00
CONT_ASSIGN53100.00
ALWAYS561700.00
CONT_ASSIGN95100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 0 1
32 0 1
36 0 1
39 0 1
42 0 1
53 0 1
56 0 1
57 0 1
58 0 1
60 0 1
61 0 1
63 0 1
64 0 1
65 0 1
69 0 1
71 0 1
73 0 1
77 0 1
78 0 1
79 0 1
89 0 1
90 0 1
91 0 1
95 0 1

Cond Coverage for Instance : tb.dut.u_to_rd_fifo.u_err
TotalCoveredPercent
Conditions3500.00
Logical3500.00
Non-Logical00
Event00

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------
-1--2--3-StatusTests
000Not Covered
001Not Covered
010Not Covered
100Not Covered 

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------
-1--2--3-StatusTests
000Not Covered
001Not Covered
010Not Covered
100Not Covered 

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       71
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       73
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       95
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered 

 LINE       95
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----
-1--2--3-StatusTests
000Not Covered
001Not Covered
010Not Covered
100Not Covered
Branch Coverage for Instance : tb.dut.u_to_rd_fifo.u_err
Line No.TotalCoveredPercent
Branches 8 0 0.00
IF 60 8 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	60	if (tl_i.a_valid)
-2-:	61	case (tl_i.a_size)
-3-:	71	(tl_i.a_address[1]) ? 
-4-:	73	(tl_i.a_address[1]) ?

Branches:
-1--2--3--4-StatusTests
1 'h0 - - Not Covered
1 'h1 1 - Not Covered
1 'h1 0 - Not Covered
1 'h1 - 1 Not Covered
1 'h1 - 0 Not Covered
1 'h00000002 - - Not Covered
1 default - - Not Covered
0 - - - Not Covered

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_err
Line No.TotalCoveredPercent
TOTAL2600.00
CONT_ASSIGN26100.00
CONT_ASSIGN27100.00
CONT_ASSIGN28100.00
CONT_ASSIGN32100.00
CONT_ASSIGN36100.00
CONT_ASSIGN39100.00
CONT_ASSIGN42100.00
CONT_ASSIGN53100.00
ALWAYS561700.00
CONT_ASSIGN95100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 0 1
27 0 1
28 0 1
32 0 1
36 0 1
39 0 1
42 0 1
53 0 1
56 0 1
57 0 1
58 0 1
60 0 1
61 0 1
63 0 1
64 0 1
65 0 1
69 0 1
71 0 1
73 0 1
77 0 1
78 0 1
79 0 1
89 0 1
90 0 1
91 0 1
95 0 1

Cond Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_err
TotalCoveredPercent
Conditions3500.00
Logical3500.00
Non-Logical00
Event00

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------
-1--2--3-StatusTests
000Not Covered
001Not Covered
010Not Covered
100Not Covered 

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------
-1--2--3-StatusTests
000Not Covered
001Not Covered
010Not Covered
100Not Covered 

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       71
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       73
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       95
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered 

 LINE       95
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----
-1--2--3-StatusTests
000Not Covered
001Not Covered
010Not Covered
100Not Covered
Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_err
Line No.TotalCoveredPercent
Branches 8 0 0.00
IF 60 8 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	60	if (tl_i.a_valid)
-2-:	61	case (tl_i.a_size)
-3-:	71	(tl_i.a_address[1]) ? 
-4-:	73	(tl_i.a_address[1]) ?

Branches:
-1--2--3--4-StatusTests
1 'h0 - - Not Covered
1 'h1 1 - Not Covered
1 'h1 0 - Not Covered
1 'h1 - 1 Not Covered
1 'h1 - 0 Not Covered
1 'h00000002 - - Not Covered
1 default - - Not Covered
0 - - - Not Covered

Line Coverage for Instance : tb.dut.u_reg_core.u_reg_if.u_err
Line No.TotalCoveredPercent
TOTAL2626100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3611100.00
CONT_ASSIGN3911100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN5311100.00
ALWAYS561717100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
32 1 1
36 1 1
39 1 1
42 1 1
53 1 1
56 1 1
57 1 1
58 1 1
60 1 1
61 1 1
63 1 1
64 1 1
65 1 1
69 1 1
71 1 1
73 1 1
77 1 1
78 1 1
79 1 1
89 1 1
90 1 1
91 1 1
95 1 1

Cond Coverage for Instance : tb.dut.u_reg_core.u_reg_if.u_err
TotalCoveredPercent
Conditions3535100.00
Logical3535100.00
Non-Logical00
Event00

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT11,T12,T5
010CoveredT11,T12,T14
100CoveredT2,T11,T4 

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------
-1--2-StatusTests
01CoveredT11,T4,T12
10CoveredT2,T11,T4
11CoveredT1,T2,T3 

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------
-1--2--3-StatusTests
000CoveredT11,T4,T12
001CoveredT1,T2,T3
010CoveredT1,T2,T3
100CoveredT1,T2,T3 

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       71
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T11,T4 

 LINE       73
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T11,T4 

 LINE       95
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------
-1--2--3-StatusTests
011CoveredT11,T12,T14
101CoveredT11,T12,T5
110CoveredT11,T4,T12
111CoveredT1,T2,T3 

 LINE       95
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----
-1--2--3-StatusTests
000CoveredT2,T11,T4
001CoveredT1,T2,T3
010CoveredT1,T2,T3
100CoveredT1,T2,T3
Branch Coverage for Instance : tb.dut.u_reg_core.u_reg_if.u_err
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 8 8 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	60	if (tl_i.a_valid)
-2-:	61	case (tl_i.a_size)
-3-:	71	(tl_i.a_address[1]) ? 
-4-:	73	(tl_i.a_address[1]) ?

Branches:
-1--2--3--4-StatusTests
1 'h0 - - Covered T1,T2,T3
1 'h1 1 - Covered T2,T11,T4
1 'h1 0 - Covered T1,T2,T3
1 'h1 - 1 Covered T2,T11,T4
1 'h1 - 0 Covered T1,T2,T3
1 'h00000002 - - Covered T1,T2,T3
1 default - - Covered T11,T12,T14
0 - - - Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_core.u_reg_if.u_err
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
dataWidthOnly32_A 215 215 0 0


dataWidthOnly32_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 215 215 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T7 1 1 0 0
T9 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_err
Line No.TotalCoveredPercent
TOTAL2626100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN3211100.00
CONT_ASSIGN3611100.00
CONT_ASSIGN3911100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN5311100.00
ALWAYS561717100.00
CONT_ASSIGN9511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
26 1 1
27 1 1
28 1 1
32 1 1
36 1 1
39 1 1
42 1 1
53 1 1
56 1 1
57 1 1
58 1 1
60 1 1
61 1 1
63 1 1
64 1 1
65 1 1
69 1 1
71 1 1
73 1 1
77 1 1
78 1 1
79 1 1
89 1 1
90 1 1
91 1 1
95 1 1

Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_err
TotalCoveredPercent
Conditions3535100.00
Logical3535100.00
Non-Logical00
Event00

 LINE       26
 EXPRESSION (tl_i.a_opcode == PutFullData)
            ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT13,T11,T4 

 LINE       27
 EXPRESSION (tl_i.a_opcode == PutPartialData)
            ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT13,T11,T4 

 LINE       28
 EXPRESSION (tl_i.a_opcode == Get)
            -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT11,T4,T7 

 LINE       39
 EXPRESSION (( ~ (opcode_allowed & a_config_allowed) ) | instr_wr_err | instr_type_err)
             --------------------1--------------------   ------2-----   -------3------
-1--2--3-StatusTests
000CoveredT11,T4,T12
001CoveredT11,T4,T12
010CoveredT11,T12,T14
100CoveredT13,T11,T4 

 LINE       39
 SUB-EXPRESSION (opcode_allowed & a_config_allowed)
                 -------1------   --------2-------
-1--2-StatusTests
01CoveredT11,T12,T14
10CoveredT13,T11,T4
11CoveredT11,T4,T12 

 LINE       42
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData) | (tl_i.a_opcode == Get))
             ---------------1--------------   ----------------2----------------   -----------3----------
-1--2--3-StatusTests
000CoveredT11,T12,T5
001CoveredT11,T4,T7
010CoveredT13,T11,T4
100CoveredT13,T11,T4 

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT13,T11,T4 

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT13,T11,T4 

 LINE       42
 SUB-EXPRESSION (tl_i.a_opcode == Get)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT11,T4,T7 

 LINE       71
 EXPRESSION (tl_i.a_address[1] ? ((~|(tl_i.a_mask & 4'b0011))) : ((~|(tl_i.a_mask & 4'b1100))))
             --------1--------
-1-StatusTests
0CoveredT11,T4,T12
1CoveredT11,T4,T12 

 LINE       73
 EXPRESSION (tl_i.a_address[1] ? ((&tl_i.a_mask[3:2])) : ((&tl_i.a_mask[1:0])))
             --------1--------
-1-StatusTests
0CoveredT11,T4,T12
1CoveredT11,T4,T12 

 LINE       95
 EXPRESSION (addr_sz_chk & mask_chk & (op_get | op_partial | fulldata_chk))
             -----1-----   ----2---   ------------------3-----------------
-1--2--3-StatusTests
011CoveredT11,T12,T5
101CoveredT11,T12,T5
110CoveredT11,T4,T12
111CoveredT11,T4,T12 

 LINE       95
 SUB-EXPRESSION (op_get | op_partial | fulldata_chk)
                 ---1--   -----2----   ------3-----
-1--2--3-StatusTests
000CoveredT13,T11,T4
001CoveredT11,T4,T12
010CoveredT13,T11,T4
100CoveredT11,T4,T7
Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_err
Line No.TotalCoveredPercent
Branches 8 8 100.00
IF 60 8 8 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_err.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	60	if (tl_i.a_valid)
-2-:	61	case (tl_i.a_size)
-3-:	71	(tl_i.a_address[1]) ? 
-4-:	73	(tl_i.a_address[1]) ?

Branches:
-1--2--3--4-StatusTests
1 'h0 - - Covered T11,T4,T12
1 'h1 1 - Covered T11,T4,T12
1 'h1 0 - Covered T11,T4,T12
1 'h1 - 1 Covered T11,T4,T12
1 'h1 - 0 Covered T11,T4,T12
1 'h00000002 - - Covered T11,T4,T12
1 default - - Covered T11,T12,T14
0 - - - Covered T13,T11,T4

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_err
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
dataWidthOnly32_A 215 215 0 0


dataWidthOnly32_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 215 215 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T7 1 1 0 0
T9 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%