Unified Coverage Report :: Module :: flash_ctrl_phy_cov_if

Module : flash_ctrl_phy_cov_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if	0.00	0.00	0.00			0.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_prim_flash_banks[0].u_prim_flash_bank

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00		0.00	0.00		gen_prim_flash_banks[1].u_prim_flash_bank

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : flash_ctrl_phy_cov_if

	Line No.	Total	Covered	Percent
TOTAL		18	0	0.00
CONT_ASSIGN	24	1	0	0.00
CONT_ASSIGN	26	1	0	0.00
ALWAYS	32	8	0	0.00
ALWAYS	43	4	0	0.00
ALWAYS	56	3	0	0.00
CONT_ASSIGN	63	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv' or '../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	0	1
26	0	1
32	0	1
33	0	1
34	0	2
35	0	2
36	0	2
			==> MISSING_ELSE
			==> MISSING_ELSE
43	0	1
44	0	1
46	0	1
47	0	1
			==> MISSING_ELSE
56	0	2
57	0	1
63	0	1

---

Cond Coverage for Module : flash_ctrl_phy_cov_if

	Total	Covered	Percent
Conditions	27	0	0.00
Logical	27	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (rd_req || prog_req || pg_erase_req || bk_erase_req)
             ---1--    ----2---    ------3-----    ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Not Covered
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Not Covered

 LINE       26
 EXPRESSION (any_req && ack)
             ---1---    -2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       36
 EXPRESSION (pg_erase_req || bk_erase_req)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       56
 EXPRESSION (((!rst_ni)) || ((!rd_buf_en)))
             -----1-----    -------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       57
 EXPRESSION (any_vld_req ? 0 : ((idle_cnt == 32'hffffffff) ? 32'hffffffff : ((idle_cnt + 32'b1))))
             -----1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       57
 SUB-EXPRESSION ((idle_cnt == 32'hffffffff) ? 32'hffffffff : ((idle_cnt + 32'b1)))
                 -------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       57
 SUB-EXPRESSION (idle_cnt == 32'hffffffff)
                -------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       63
 EXPRESSION ((cur_cmd == READ) && (prv_cmd_q == READ))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       63
 SUB-EXPRESSION (cur_cmd == READ)
                --------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       63
 SUB-EXPRESSION (prv_cmd_q == READ)
                ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Module : flash_ctrl_phy_cov_if

	Line No.	Total	Covered	Percent
Branches		12	0	0.00
IF	33	5	0	0.00
IF	43	3	0	0.00
IF	56	4	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv' or '../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	33	if (any_vld_req)
-2-:	34	if (rd_req)
-3-:	35	if (prog_req)
-4-:	36	if ((pg_erase_req || bk_erase_req))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Not Covered
1	0	1	-	Not Covered
1	0	0	1	Not Covered
1	0	0	0	Not Covered
0	-	-	-	Not Covered

	LineNo.	Expression
-1-:	43	if ((!rst_ni))
-2-:	46	if (any_vld_req)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	56	if (((!rst_ni) || (!rd_buf_en)))
-2-:	57	(any_vld_req) ? 
-3-:	57	((idle_cnt == 32'hffffffff)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if

	Line No.	Total	Covered	Percent
TOTAL		18	0	0.00
CONT_ASSIGN	24	1	0	0.00
CONT_ASSIGN	26	1	0	0.00
ALWAYS	32	8	0	0.00
ALWAYS	43	4	0	0.00
ALWAYS	56	3	0	0.00
CONT_ASSIGN	63	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv' or '../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	0	1
26	0	1
32	0	1
33	0	1
34	0	2
35	0	2
36	0	2
			==> MISSING_ELSE
			==> MISSING_ELSE
43	0	1
44	0	1
46	0	1
47	0	1
			==> MISSING_ELSE
56	0	2
57	0	1
63	0	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if

	Total	Covered	Percent
Conditions	27	0	0.00
Logical	27	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (rd_req || prog_req || pg_erase_req || bk_erase_req)
             ---1--    ----2---    ------3-----    ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Not Covered
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Not Covered

 LINE       26
 EXPRESSION (any_req && ack)
             ---1---    -2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       36
 EXPRESSION (pg_erase_req || bk_erase_req)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       56
 EXPRESSION (((!rst_ni)) || ((!rd_buf_en)))
             -----1-----    -------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       57
 EXPRESSION (any_vld_req ? 0 : ((idle_cnt == 32'hffffffff) ? 32'hffffffff : ((idle_cnt + 32'b1))))
             -----1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       57
 SUB-EXPRESSION ((idle_cnt == 32'hffffffff) ? 32'hffffffff : ((idle_cnt + 32'b1)))
                 -------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       57
 SUB-EXPRESSION (idle_cnt == 32'hffffffff)
                -------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       63
 EXPRESSION ((cur_cmd == READ) && (prv_cmd_q == READ))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       63
 SUB-EXPRESSION (cur_cmd == READ)
                --------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       63
 SUB-EXPRESSION (prv_cmd_q == READ)
                ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if

	Line No.	Total	Covered	Percent
Branches		12	0	0.00
IF	33	5	0	0.00
IF	43	3	0	0.00
IF	56	4	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv' or '../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	33	if (any_vld_req)
-2-:	34	if (rd_req)
-3-:	35	if (prog_req)
-4-:	36	if ((pg_erase_req || bk_erase_req))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Not Covered
1	0	1	-	Not Covered
1	0	0	1	Not Covered
1	0	0	0	Not Covered
0	-	-	-	Not Covered

	LineNo.	Expression
-1-:	43	if ((!rst_ni))
-2-:	46	if (any_vld_req)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	56	if (((!rst_ni) || (!rd_buf_en)))
-2-:	57	(any_vld_req) ? 
-3-:	57	((idle_cnt == 32'hffffffff)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if

	Line No.	Total	Covered	Percent
TOTAL		18	0	0.00
CONT_ASSIGN	24	1	0	0.00
CONT_ASSIGN	26	1	0	0.00
ALWAYS	32	8	0	0.00
ALWAYS	43	4	0	0.00
ALWAYS	56	3	0	0.00
CONT_ASSIGN	63	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv' or '../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
24	0	1
26	0	1
32	0	1
33	0	1
34	0	2
35	0	2
36	0	2
			==> MISSING_ELSE
			==> MISSING_ELSE
43	0	1
44	0	1
46	0	1
47	0	1
			==> MISSING_ELSE
56	0	2
57	0	1
63	0	1

---

Cond Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if

	Total	Covered	Percent
Conditions	27	0	0.00
Logical	27	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       24
 EXPRESSION (rd_req || prog_req || pg_erase_req || bk_erase_req)
             ---1--    ----2---    ------3-----    ------4-----

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Not Covered
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Not Covered

 LINE       26
 EXPRESSION (any_req && ack)
             ---1---    -2-

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       36
 EXPRESSION (pg_erase_req || bk_erase_req)
             ------1-----    ------2-----

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       56
 EXPRESSION (((!rst_ni)) || ((!rd_buf_en)))
             -----1-----    -------2------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       57
 EXPRESSION (any_vld_req ? 0 : ((idle_cnt == 32'hffffffff) ? 32'hffffffff : ((idle_cnt + 32'b1))))
             -----1-----

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       57
 SUB-EXPRESSION ((idle_cnt == 32'hffffffff) ? 32'hffffffff : ((idle_cnt + 32'b1)))
                 -------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       57
 SUB-EXPRESSION (idle_cnt == 32'hffffffff)
                -------------1------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       63
 EXPRESSION ((cur_cmd == READ) && (prv_cmd_q == READ))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       63
 SUB-EXPRESSION (cur_cmd == READ)
                --------1--------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       63
 SUB-EXPRESSION (prv_cmd_q == READ)
                ---------1---------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_phy_cov_if

	Line No.	Total	Covered	Percent
Branches		12	0	0.00
IF	33	5	0	0.00
IF	43	3	0	0.00
IF	56	4	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv' or '../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	33	if (any_vld_req)
-2-:	34	if (rd_req)
-3-:	35	if (prog_req)
-4-:	36	if ((pg_erase_req || bk_erase_req))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	1	-	-	Not Covered
1	0	1	-	Not Covered
1	0	0	1	Not Covered
1	0	0	0	Not Covered
0	-	-	-	Not Covered

	LineNo.	Expression
-1-:	43	if ((!rst_ni))
-2-:	46	if (any_vld_req)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	56	if (((!rst_ni) || (!rd_buf_en)))
-2-:	57	(any_vld_req) ? 
-3-:	57	((idle_cnt == 32'hffffffff)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered