Module Definition
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Module : prim_secded_inv_64_57_enc
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_enc.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.gen_rsp_intg.u_rsp_gen 0.00 0.00
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.gen_rsp_intg.u_rsp_gen 0.00 0.00
tb.dut.u_tl_adapter_eflash.u_rsp_gen.gen_rsp_intg.u_rsp_gen 0.00 0.00
tb.dut.u_reg_core.u_rsp_intg_gen.gen_rsp_intg.u_rsp_gen 100.00 100.00
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.gen_rsp_intg.u_rsp_gen 100.00 100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.gen_rsp_intg.u_rsp_gen 100.00 100.00


Module Instance : tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.gen_rsp_intg.u_rsp_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
0.00 0.00 u_intg_gen


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.gen_rsp_intg.u_rsp_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
0.00 0.00 u_intg_gen


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_tl_adapter_eflash.u_rsp_gen.gen_rsp_intg.u_rsp_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
0.00 0.00 u_rsp_gen


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_rsp_intg_gen.gen_rsp_intg.u_rsp_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_rsp_intg_gen


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.gen_rsp_intg.u_rsp_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_intg_gen


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.gen_rsp_intg.u_rsp_gen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 u_rsp_intg_gen


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_secded_inv_64_57_enc
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS1399100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_enc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
13 1 1
14 1 1
15 1 1
16 1 1
17 1 1
18 1 1
19 1 1
20 1 1
21 1 1

Line Coverage for Instance : tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.gen_rsp_intg.u_rsp_gen
Line No.TotalCoveredPercent
TOTAL900.00
ALWAYS13900.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_enc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
13 0 1
14 0 1
15 0 1
16 0 1
17 0 1
18 0 1
19 0 1
20 0 1
21 0 1

Line Coverage for Instance : tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.gen_rsp_intg.u_rsp_gen
Line No.TotalCoveredPercent
TOTAL900.00
ALWAYS13900.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_enc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
13 0 1
14 0 1
15 0 1
16 0 1
17 0 1
18 0 1
19 0 1
20 0 1
21 0 1

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rsp_gen.gen_rsp_intg.u_rsp_gen
Line No.TotalCoveredPercent
TOTAL900.00
ALWAYS13900.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_enc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
13 0 1
14 0 1
15 0 1
16 0 1
17 0 1
18 0 1
19 0 1
20 0 1
21 0 1

Line Coverage for Instance : tb.dut.u_reg_core.u_rsp_intg_gen.gen_rsp_intg.u_rsp_gen
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS1399100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_enc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
13 1 1
14 1 1
15 1 1
16 1 1
17 1 1
18 1 1
19 1 1
20 1 1
21 1 1

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.gen_rsp_intg.u_rsp_gen
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS1399100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_enc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
13 1 1
14 1 1
15 1 1
16 1 1
17 1 1
18 1 1
19 1 1
20 1 1
21 1 1

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.gen_rsp_intg.u_rsp_gen
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS1399100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_enc.sv' or '../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_enc.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
13 1 1
14 1 1
15 1 1
16 1 1
17 1 1
18 1 1
19 1 1
20 1 1
21 1 1

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