Unified Coverage Report :: Module :: prim_prince

Module : prim_prince

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_cipher_0/rtl/prim_prince.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.gen_prince.u_cipher	0.00			0.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.gen_prince.u_cipher	0.00			0.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.gen_prince.u_cipher

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_scramble

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.gen_prince.u_cipher

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_scramble

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_prince

	Total	Covered	Percent
Totals	8	0	0.00
Total Bits	522	0	0.00
Total Bits 0->1	261	0	0.00
Total Bits 1->0	261	0	0.00

Ports	8	0	0.00
Port Bits	522	0	0.00
Port Bits 0->1	261	0	0.00
Port Bits 1->0	261	0	0.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	No	No		No		INPUT
rst_ni	No	No		No		INPUT
valid_i	No	No		No		INPUT
data_i[63:0]	No	No		No		INPUT
key_i[127:0]	No	No		No		INPUT
dec_i	No	No		No		INPUT
valid_o	No	No		No		OUTPUT
data_o[63:0]	No	No		No		OUTPUT

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_scramble.gen_prince.u_cipher

Toggle Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_scramble.gen_prince.u_cipher