Line Coverage for Module : 
flash_mp_data_region_sel ( parameter Regions=9 ) 
Line Coverage for Module self-instances : 
 | Line No. | Total | Covered | Percent | 
| TOTAL |  | 16 | 0 | 0.00 | 
| CONT_ASSIGN | 28 | 1 | 0 | 0.00 | 
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 | 
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 | 
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 | 
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 | 
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 | 
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 | 
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 | 
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 | 
| ALWAYS | 35 | 0 | 0 |  | 
| ALWAYS | 35 | 3 | 0 | 0.00 | 
| ALWAYS | 49 | 4 | 0 | 0.00 | 
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements |  | 
| 28 | 
0 | 
1 | 
| 30 | 
0 | 
8 | 
| 35 | 
0 | 
1 | 
| 36 | 
0 | 
1 | 
| 39 | 
0 | 
1 | 
| 49 | 
0 | 
1 | 
| 50 | 
0 | 
1 | 
| 51 | 
0 | 
1 | 
| 52 | 
0 | 
1 | 
 | 
 | 
 | 
==>  MISSING_ELSE | 
Line Coverage for Module : 
flash_mp_data_region_sel ( parameter Regions=1 ) 
Line Coverage for Module self-instances : 
 | Line No. | Total | Covered | Percent | 
| TOTAL |  | 8 | 0 | 0.00 | 
| CONT_ASSIGN | 28 | 1 | 0 | 0.00 | 
| ALWAYS | 35 | 0 | 0 |  | 
| ALWAYS | 35 | 3 | 0 | 0.00 | 
| ALWAYS | 49 | 4 | 0 | 0.00 | 
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements |  | 
| 28 | 
0 | 
1 | 
| 35 | 
0 | 
1 | 
| 36 | 
0 | 
1 | 
| 39 | 
0 | 
1 | 
| 49 | 
0 | 
1 | 
| 50 | 
0 | 
1 | 
| 51 | 
0 | 
1 | 
| 52 | 
0 | 
1 | 
 | 
 | 
 | 
==>  MISSING_ELSE | 
Cond Coverage for Module : 
flash_mp_data_region_sel
 | Total | Covered | Percent | 
| Conditions | 24 | 0 | 0.00 | 
| Logical | 24 | 0 | 0.00 | 
| Non-Logical | 0 | 0 |  | 
| Event | 0 | 0 |  | 
 LINE       30
 EXPRESSION (region_match[1] & ((~|region_match[0])))
             -------1-------   ----------2----------
| -1- | -2- | Status | Tests | 
| 0 | 1 | Not Covered |  | 
| 1 | 0 | Not Covered |  | 
| 1 | 1 | Not Covered |  | 
 LINE       30
 EXPRESSION (region_match[2] & ((~|region_match[(2 - 1):0])))
             -------1-------   --------------2--------------
| -1- | -2- | Status | Tests | 
| 0 | 1 | Not Covered |  | 
| 1 | 0 | Not Covered |  | 
| 1 | 1 | Not Covered |  | 
 LINE       30
 EXPRESSION (region_match[3] & ((~|region_match[(3 - 1):0])))
             -------1-------   --------------2--------------
| -1- | -2- | Status | Tests | 
| 0 | 1 | Not Covered |  | 
| 1 | 0 | Not Covered |  | 
| 1 | 1 | Not Covered |  | 
 LINE       30
 EXPRESSION (region_match[4] & ((~|region_match[(4 - 1):0])))
             -------1-------   --------------2--------------
| -1- | -2- | Status | Tests | 
| 0 | 1 | Not Covered |  | 
| 1 | 0 | Not Covered |  | 
| 1 | 1 | Not Covered |  | 
 LINE       30
 EXPRESSION (region_match[5] & ((~|region_match[(5 - 1):0])))
             -------1-------   --------------2--------------
| -1- | -2- | Status | Tests | 
| 0 | 1 | Not Covered |  | 
| 1 | 0 | Not Covered |  | 
| 1 | 1 | Not Covered |  | 
 LINE       30
 EXPRESSION (region_match[6] & ((~|region_match[(6 - 1):0])))
             -------1-------   --------------2--------------
| -1- | -2- | Status | Tests | 
| 0 | 1 | Not Covered |  | 
| 1 | 0 | Not Covered |  | 
| 1 | 1 | Not Covered |  | 
 LINE       30
 EXPRESSION (region_match[7] & ((~|region_match[(7 - 1):0])))
             -------1-------   --------------2--------------
| -1- | -2- | Status | Tests | 
| 0 | 1 | Not Covered |  | 
| 1 | 0 | Not Covered |  | 
| 1 | 1 | Not Covered |  | 
 LINE       30
 EXPRESSION (region_match[8] & ((~|region_match[(8 - 1):0])))
             -------1-------   --------------2--------------
| -1- | -2- | Status | Tests | 
| 0 | 1 | Not Covered |  | 
| 1 | 0 | Not Covered |  | 
| 1 | 1 | Not Covered |  | 
Branch Coverage for Module : 
flash_mp_data_region_sel
 | Line No. | Total | Covered | Percent | 
| Branches | 
 | 
2 | 
0 | 
0.00   | 
| IF | 
51 | 
2 | 
0 | 
0.00   | 
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv was not found/opened, so annotated branch coverage report could not be generated.
	LineNo.	Expression
-1-:	51	if (region_sel[i])
Branches:
| -1- | Status | Tests | 
| 1 | 
Not Covered | 
 | 
| 0 | 
Not Covered | 
 | 
 
Line Coverage for Instance : tb.dut.u_flash_mp.u_sw_sel
 | Line No. | Total | Covered | Percent | 
| TOTAL |  | 16 | 0 | 0.00 | 
| CONT_ASSIGN | 28 | 1 | 0 | 0.00 | 
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 | 
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 | 
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 | 
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 | 
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 | 
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 | 
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 | 
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 | 
| ALWAYS | 35 | 0 | 0 |  | 
| ALWAYS | 35 | 3 | 0 | 0.00 | 
| ALWAYS | 49 | 4 | 0 | 0.00 | 
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements |  | 
| 28 | 
0 | 
1 | 
| 30 | 
0 | 
8 | 
| 35 | 
0 | 
1 | 
| 36 | 
0 | 
1 | 
| 39 | 
0 | 
1 | 
| 49 | 
0 | 
1 | 
| 50 | 
0 | 
1 | 
| 51 | 
0 | 
1 | 
| 52 | 
0 | 
1 | 
 | 
 | 
 | 
==>  MISSING_ELSE | 
Cond Coverage for Instance : tb.dut.u_flash_mp.u_sw_sel
 | Total | Covered | Percent | 
| Conditions | 24 | 0 | 0.00 | 
| Logical | 24 | 0 | 0.00 | 
| Non-Logical | 0 | 0 |  | 
| Event | 0 | 0 |  | 
 LINE       30
 EXPRESSION (region_match[1] & ((~|region_match[0])))
             -------1-------   ----------2----------
| -1- | -2- | Status | Tests | 
| 0 | 1 | Not Covered |  | 
| 1 | 0 | Not Covered |  | 
| 1 | 1 | Not Covered |  | 
 LINE       30
 EXPRESSION (region_match[2] & ((~|region_match[(2 - 1):0])))
             -------1-------   --------------2--------------
| -1- | -2- | Status | Tests | 
| 0 | 1 | Not Covered |  | 
| 1 | 0 | Not Covered |  | 
| 1 | 1 | Not Covered |  | 
 LINE       30
 EXPRESSION (region_match[3] & ((~|region_match[(3 - 1):0])))
             -------1-------   --------------2--------------
| -1- | -2- | Status | Tests | 
| 0 | 1 | Not Covered |  | 
| 1 | 0 | Not Covered |  | 
| 1 | 1 | Not Covered |  | 
 LINE       30
 EXPRESSION (region_match[4] & ((~|region_match[(4 - 1):0])))
             -------1-------   --------------2--------------
| -1- | -2- | Status | Tests | 
| 0 | 1 | Not Covered |  | 
| 1 | 0 | Not Covered |  | 
| 1 | 1 | Not Covered |  | 
 LINE       30
 EXPRESSION (region_match[5] & ((~|region_match[(5 - 1):0])))
             -------1-------   --------------2--------------
| -1- | -2- | Status | Tests | 
| 0 | 1 | Not Covered |  | 
| 1 | 0 | Not Covered |  | 
| 1 | 1 | Not Covered |  | 
 LINE       30
 EXPRESSION (region_match[6] & ((~|region_match[(6 - 1):0])))
             -------1-------   --------------2--------------
| -1- | -2- | Status | Tests | 
| 0 | 1 | Not Covered |  | 
| 1 | 0 | Not Covered |  | 
| 1 | 1 | Not Covered |  | 
 LINE       30
 EXPRESSION (region_match[7] & ((~|region_match[(7 - 1):0])))
             -------1-------   --------------2--------------
| -1- | -2- | Status | Tests | 
| 0 | 1 | Not Covered |  | 
| 1 | 0 | Not Covered |  | 
| 1 | 1 | Not Covered |  | 
 LINE       30
 EXPRESSION (region_match[8] & ((~|region_match[(8 - 1):0])))
             -------1-------   --------------2--------------
| -1- | -2- | Status | Tests | 
| 0 | 1 | Not Covered |  | 
| 1 | 0 | Not Covered |  | 
| 1 | 1 | Not Covered |  | 
Branch Coverage for Instance : tb.dut.u_flash_mp.u_sw_sel
 | Line No. | Total | Covered | Percent | 
| Branches | 
 | 
2 | 
0 | 
0.00   | 
| IF | 
51 | 
2 | 
0 | 
0.00   | 
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv was not found/opened, so annotated branch coverage report could not be generated.
	LineNo.	Expression
-1-:	51	if (region_sel[i])
Branches:
| -1- | Status | Tests | 
| 1 | 
Not Covered | 
 | 
| 0 | 
Not Covered | 
 | 
 
Line Coverage for Instance : tb.dut.u_flash_mp.u_hw_sel
 | Line No. | Total | Covered | Percent | 
| TOTAL |  | 8 | 0 | 0.00 | 
| CONT_ASSIGN | 28 | 1 | 0 | 0.00 | 
| ALWAYS | 35 | 0 | 0 |  | 
| ALWAYS | 35 | 3 | 0 | 0.00 | 
| ALWAYS | 49 | 4 | 0 | 0.00 | 
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements |  | 
| 28 | 
0 | 
1 | 
| 35 | 
0 | 
1 | 
| 36 | 
0 | 
1 | 
| 39 | 
0 | 
1 | 
| 49 | 
0 | 
1 | 
| 50 | 
0 | 
1 | 
| 51 | 
0 | 
1 | 
| 52 | 
0 | 
1 | 
 | 
 | 
 | 
==>  MISSING_ELSE | 
Branch Coverage for Instance : tb.dut.u_flash_mp.u_hw_sel
 | Line No. | Total | Covered | Percent | 
| Branches | 
 | 
2 | 
0 | 
0.00   | 
| IF | 
51 | 
2 | 
0 | 
0.00   | 
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv was not found/opened, so annotated branch coverage report could not be generated.
	LineNo.	Expression
-1-:	51	if (region_sel[i])
Branches:
| -1- | Status | Tests | 
| 1 | 
Not Covered | 
 | 
| 0 | 
Not Covered | 
 | 
 
Line Coverage for Instance : tb.dut.u_eflash.u_region_sel
 | Line No. | Total | Covered | Percent | 
| TOTAL |  | 16 | 0 | 0.00 | 
| CONT_ASSIGN | 28 | 1 | 0 | 0.00 | 
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 | 
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 | 
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 | 
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 | 
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 | 
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 | 
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 | 
| CONT_ASSIGN | 30 | 1 | 0 | 0.00 | 
| ALWAYS | 35 | 0 | 0 |  | 
| ALWAYS | 35 | 3 | 0 | 0.00 | 
| ALWAYS | 49 | 4 | 0 | 0.00 | 
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' was not found, so annotated line coverage report could not be generated.
| Line No. | Covered | Statements |  | 
| 28 | 
0 | 
1 | 
| 30 | 
0 | 
8 | 
| 35 | 
0 | 
1 | 
| 36 | 
0 | 
1 | 
| 39 | 
0 | 
1 | 
| 49 | 
0 | 
1 | 
| 50 | 
0 | 
1 | 
| 51 | 
0 | 
1 | 
| 52 | 
0 | 
1 | 
 | 
 | 
 | 
==>  MISSING_ELSE | 
Cond Coverage for Instance : tb.dut.u_eflash.u_region_sel
 | Total | Covered | Percent | 
| Conditions | 24 | 0 | 0.00 | 
| Logical | 24 | 0 | 0.00 | 
| Non-Logical | 0 | 0 |  | 
| Event | 0 | 0 |  | 
 LINE       30
 EXPRESSION (region_match[1] & ((~|region_match[0])))
             -------1-------   ----------2----------
| -1- | -2- | Status | Tests | 
| 0 | 1 | Not Covered |  | 
| 1 | 0 | Not Covered |  | 
| 1 | 1 | Not Covered |  | 
 LINE       30
 EXPRESSION (region_match[2] & ((~|region_match[(2 - 1):0])))
             -------1-------   --------------2--------------
| -1- | -2- | Status | Tests | 
| 0 | 1 | Not Covered |  | 
| 1 | 0 | Not Covered |  | 
| 1 | 1 | Not Covered |  | 
 LINE       30
 EXPRESSION (region_match[3] & ((~|region_match[(3 - 1):0])))
             -------1-------   --------------2--------------
| -1- | -2- | Status | Tests | 
| 0 | 1 | Not Covered |  | 
| 1 | 0 | Not Covered |  | 
| 1 | 1 | Not Covered |  | 
 LINE       30
 EXPRESSION (region_match[4] & ((~|region_match[(4 - 1):0])))
             -------1-------   --------------2--------------
| -1- | -2- | Status | Tests | 
| 0 | 1 | Not Covered |  | 
| 1 | 0 | Not Covered |  | 
| 1 | 1 | Not Covered |  | 
 LINE       30
 EXPRESSION (region_match[5] & ((~|region_match[(5 - 1):0])))
             -------1-------   --------------2--------------
| -1- | -2- | Status | Tests | 
| 0 | 1 | Not Covered |  | 
| 1 | 0 | Not Covered |  | 
| 1 | 1 | Not Covered |  | 
 LINE       30
 EXPRESSION (region_match[6] & ((~|region_match[(6 - 1):0])))
             -------1-------   --------------2--------------
| -1- | -2- | Status | Tests | 
| 0 | 1 | Not Covered |  | 
| 1 | 0 | Not Covered |  | 
| 1 | 1 | Not Covered |  | 
 LINE       30
 EXPRESSION (region_match[7] & ((~|region_match[(7 - 1):0])))
             -------1-------   --------------2--------------
| -1- | -2- | Status | Tests | 
| 0 | 1 | Not Covered |  | 
| 1 | 0 | Not Covered |  | 
| 1 | 1 | Not Covered |  | 
 LINE       30
 EXPRESSION (region_match[8] & ((~|region_match[(8 - 1):0])))
             -------1-------   --------------2--------------
| -1- | -2- | Status | Tests | 
| 0 | 1 | Not Covered |  | 
| 1 | 0 | Not Covered |  | 
| 1 | 1 | Not Covered |  | 
Branch Coverage for Instance : tb.dut.u_eflash.u_region_sel
 | Line No. | Total | Covered | Percent | 
| Branches | 
 | 
2 | 
0 | 
0.00   | 
| IF | 
51 | 
2 | 
0 | 
0.00   | 
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_mp_data_region_sel.sv was not found/opened, so annotated branch coverage report could not be generated.
	LineNo.	Expression
-1-:	51	if (region_sel[i])
Branches:
| -1- | Status | Tests | 
| 1 | 
Not Covered | 
 | 
| 0 | 
Not Covered | 
 |