Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : flash_ctrl_prog
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_prog.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_flash_ctrl_prog 0.00 0.00 0.00 0.00


Module Instance : tb.dut.u_flash_ctrl_prog

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
16.65 0.00 0.00 66.62 0.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_cnt 0.00 0.00

Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : flash_ctrl_prog
Line No.TotalCoveredPercent
TOTAL5400.00
ALWAYS55300.00
ALWAYS90400.00
CONT_ASSIGN97100.00
CONT_ASSIGN98100.00
ALWAYS101500.00
CONT_ASSIGN112100.00
CONT_ASSIGN122100.00
CONT_ASSIGN123100.00
CONT_ASSIGN124100.00
CONT_ASSIGN125100.00
CONT_ASSIGN126100.00
ALWAYS1322600.00
CONT_ASSIGN183100.00
CONT_ASSIGN184100.00
CONT_ASSIGN185100.00
CONT_ASSIGN186100.00
CONT_ASSIGN187100.00
CONT_ASSIGN188100.00
CONT_ASSIGN189100.00
CONT_ASSIGN193100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_prog.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
55 0 1
56 0 1
58 0 1
90 0 1
91 0 1
92 0 1
93 0 1
==> MISSING_ELSE
97 0 1
98 0 1
101 0 1
102 0 1
103 0 1
104 0 1
106 0 1
112 0 1
122 0 1
123 0 1
124 0 1
125 0 1
126 0 1
132 0 1
133 0 1
134 0 1
135 0 1
136 0 1
138 0 1
144 0 1
146 0 1
148 0 1
150 0 1
152 0 1
153 0 1
154 0 1
155 0 1
157 0 1
158 0 1
160 0 1
==> MISSING_ELSE
164 0 1
165 0 1
166 0 1
167 0 1
168 0 1
==> MISSING_ELSE
172 0 1
174 0 1
175 0 1
176 0 1
==> MISSING_ELSE
183 0 1
184 0 1
185 0 1
186 0 1
187 0 1
188 0 1
189 0 1
193 0 1

Cond Coverage for Module : flash_ctrl_prog
TotalCoveredPercent
Conditions3400.00
Logical3400.00
Non-Logical00
Event00

 LINE       74
 EXPRESSION (op_start_i && op_done_o)
             -----1----    ----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       92
 EXPRESSION (((~|op_err_q)) && ((|op_err_d)))
             -------1------    ------2------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       97
 EXPRESSION (flash_req_o && flash_done_i)
             -----1-----    ------2-----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       103
 EXPRESSION (op_start_i && op_done_o)
             -----1----    ----2----
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       125
 EXPRESSION (start_window != end_window)
            --------------1-------------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       126
 EXPRESSION (pgm_res_err | op_addr_oob_i)
             -----1-----   ------2------
-1--2-StatusTests
00Not Covered
01Unreachable
10Not Covered 

 LINE       148
 EXPRESSION (op_start_i && prog_type_avail && ((!win_err)))
             -----1----    -------2-------    ------3-----
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111Not Covered 

 LINE       160
 EXPRESSION (((|op_err_d)) ? StErr : StNorm)
             ------1------
-1-StatusTests
0Not Covered
1Not Covered 

 LINE       164
 EXPRESSION (op_start_i && (((!prog_type_avail)) || win_err))
             -----1----    ----------------2----------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       164
 SUB-EXPRESSION (((!prog_type_avail)) || win_err)
                 ----------1---------    ---2---
-1--2-StatusTests
00Not Covered
01Not Covered
10Not Covered 

 LINE       174
 EXPRESSION (data_rdy_i && cnt_hit)
             -----1----    ---2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered 

 LINE       187
 EXPRESSION (flash_req_o & cnt_hit)
             -----1-----   ---2---
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered
Branch Coverage for Module : flash_ctrl_prog
Line No.TotalCoveredPercent
Branches 18 0 0.00
IF 55 2 0 0.00
IF 90 3 0 0.00
IF 101 3 0 0.00
CASE 138 10 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_prog.sv' or '../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_prog.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	55	if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered 



	LineNo.	Expression
-1-:	90	if ((!rst_ni))
-2-:	92	if (((~|op_err_q) && (|op_err_d)))

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered 



	LineNo.	Expression
-1-:	101	if ((!rst_ni))
-2-:	103	if ((op_start_i && op_done_o))

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered 



	LineNo.	Expression
-1-:	138	case (st_q)
-2-:	144	if (cnt_err_o)
-3-:	148	if (((op_start_i && prog_type_avail) && (!win_err)))
-4-:	152	if (txn_done)
-5-:	157	if (cnt_hit)
-6-:	160	((|op_err_d)) ? 
-7-:	164	if ((op_start_i && ((!prog_type_avail) || win_err)))
-8-:	174	if ((data_rdy_i && cnt_hit))

Branches:
-1--2--3--4--5--6--7--8-StatusTests
StNorm 1 - - - - - - Not Covered
StNorm 0 1 1 1 - - - Not Covered
StNorm 0 1 1 0 1 - - Not Covered
StNorm 0 1 1 0 0 - - Not Covered
StNorm 0 1 0 - - - - Not Covered
StNorm 0 0 - - - 1 - Not Covered
StNorm 0 0 - - - 0 - Not Covered
StErr - - - - - - 1 Not Covered
StErr - - - - - - 0 Not Covered
default - - - - - - - Not Covered

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%