Unified Coverage Report :: Module :: prim_fifo_sync_cnt

Module : prim_fifo_sync_cnt

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_to_prog_fifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt	0.00	0.00				0.00
tb.dut.u_to_prog_fifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt	0.00	0.00				0.00
tb.dut.u_to_prog_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt	0.00	0.00				0.00
tb.dut.u_prog_fifo.gen_normal_fifo.u_fifo_cnt	0.00	0.00				0.00
tb.dut.u_to_rd_fifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt	0.00	0.00				0.00
tb.dut.u_to_rd_fifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt	0.00	0.00				0.00
tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt	0.00	0.00	0.00
tb.dut.u_sw_rd_fifo.gen_normal_fifo.u_fifo_cnt	0.00	0.00				0.00
tb.dut.u_tl_adapter_eflash.u_reqfifo.gen_normal_fifo.u_fifo_cnt	0.00	0.00				0.00
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt	0.00	0.00				0.00
tb.dut.u_tl_adapter_eflash.u_rspfifo.gen_normal_fifo.u_fifo_cnt	0.00	0.00				0.00
tb.dut.u_eflash.u_bank_sequence_fifo.gen_normal_fifo.u_fifo_cnt	0.00	0.00				0.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.u_fifo_cnt	0.00	0.00				0.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.u_fifo_cnt	0.00	0.00				0.00
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt	0.00	0.00	0.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt	0.00	0.00	0.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt	0.00	0.00	0.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.gen_normal_fifo.u_fifo_cnt	0.00	0.00				0.00
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt	0.00	0.00	0.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt	0.00	0.00	0.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt	0.00	0.00	0.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.gen_normal_fifo.u_fifo_cnt	0.00	0.00				0.00

---

Module Instance : tb.dut.u_to_prog_fifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_reqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_to_prog_fifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_sramreqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_to_prog_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_rspfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prog_fifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_prog_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_to_rd_fifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_reqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_to_rd_fifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_sramreqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_rspfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_secure_ptrs.u_rptr	0.00			0.00
gen_secure_ptrs.u_wptr	0.00			0.00

---

Module Instance : tb.dut.u_sw_rd_fifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_sw_rd_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_reqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_sramreqfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_rspfifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_bank_sequence_fifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_bank_sequence_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_cmd_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_cmd_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		gen_flash_cores[0].u_host_rsp_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_secure_ptrs.u_rptr	0.00			0.00
gen_secure_ptrs.u_wptr	0.00			0.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_rsp_order_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_secure_ptrs.u_rptr	0.00			0.00
gen_secure_ptrs.u_wptr	0.00			0.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_rd_storage

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_secure_ptrs.u_rptr	0.00			0.00
gen_secure_ptrs.u_wptr	0.00			0.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_mask_storage

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		gen_flash_cores[1].u_host_rsp_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_secure_ptrs.u_rptr	0.00			0.00
gen_secure_ptrs.u_wptr	0.00			0.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_rsp_order_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_secure_ptrs.u_rptr	0.00			0.00
gen_secure_ptrs.u_wptr	0.00			0.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_rd_storage

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_secure_ptrs.u_rptr	0.00			0.00
gen_secure_ptrs.u_wptr	0.00			0.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.gen_normal_fifo.u_fifo_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00				0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_mask_storage

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=1,Width=2,Secure=0 + Depth=2,Width=2,Secure=0 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.u_to_prog_fifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
0.00	0.00

tb.dut.u_to_prog_fifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
0.00	0.00

tb.dut.u_to_prog_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
0.00	0.00

tb.dut.u_to_rd_fifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
0.00	0.00

tb.dut.u_to_rd_fifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
0.00	0.00

tb.dut.u_tl_adapter_eflash.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
0.00	0.00

tb.dut.u_tl_adapter_eflash.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
0.00	0.00

tb.dut.u_tl_adapter_eflash.u_rspfifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
0.00	0.00

tb.dut.u_eflash.u_bank_sequence_fifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
0.00	0.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
0.00	0.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
0.00	0.00

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
0.00	0.00

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	0	0.00
CONT_ASSIGN	29	1	0	0.00
CONT_ASSIGN	30	1	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	33	1	0	0.00
ALWAYS	76	7	0	0.00
ALWAYS	88	7	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	0	1
30	0	1
32	0	1
33	0	1
76	0	1
77	0	1
78	0	1
79		unreachable
80	0	1
81	0	1
82	0	1
83	0	1
			==> MISSING_ELSE
88	0	1
89	0	1
90	0	1
91		unreachable
92	0	1
93	0	1
94	0	1
95	0	1
			==> MISSING_ELSE

---

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=1,Width=2,Secure=1 + Depth=2,Width=2,Secure=1 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
0.00	0.00

tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
0.00	0.00

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
0.00	0.00

tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
0.00	0.00

tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
0.00	0.00

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt

SCORE	LINE
0.00	0.00

tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		5	0	0.00
CONT_ASSIGN	29	1	0	0.00
CONT_ASSIGN	30	1	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	33	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	0	1
30	0	1
32	0	1
33	0	1
72	0	1

---

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=4,Width=3,Secure=0 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.u_prog_fifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		20	0	0.00
CONT_ASSIGN	29	1	0	0.00
CONT_ASSIGN	30	1	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	33	1	0	0.00
ALWAYS	76	8	0	0.00
ALWAYS	88	8	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	0	1
30	0	1
32	0	1
33	0	1
76	0	1
77	0	1
78	0	1
79	0	1
80	0	1
81	0	1
82	0	1
83	0	1
			==> MISSING_ELSE
88	0	1
89	0	1
90	0	1
91	0	1
92	0	1
93	0	1
94	0	1
95	0	1
			==> MISSING_ELSE

---

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=16,Width=5,Secure=0 )
Line Coverage for Module self-instances :

SCORE	LINE
0.00	0.00

tb.dut.u_sw_rd_fifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		20	0	0.00
CONT_ASSIGN	29	1	0	0.00
CONT_ASSIGN	30	1	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	33	1	0	0.00
ALWAYS	76	8	0	0.00
ALWAYS	88	8	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	0	1
30	0	1
32	0	1
33	0	1
76	0	1
77	0	1
78	0	1
79	0	1
80	0	1
81	0	1
82	0	1
83	0	1
			==> MISSING_ELSE
88	0	1
89	0	1
90	0	1
91	0	1
92	0	1
93	0	1
94	0	1
95	0	1
			==> MISSING_ELSE

---

Cond Coverage for Module : prim_fifo_sync_cnt

	Total	Covered	Percent
Conditions	3	0	0.00
Logical	3	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       72
 EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
             ------------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

---

Branch Coverage for Module : prim_fifo_sync_cnt

	Line No.	Total	Covered	Percent
Branches		10	0	0.00
IF	76	5	0	0.00
IF	88	5	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	78	if (clr_i)
-3-:	80	if (wptr_wrap)
-4-:	82	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Not Covered
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	88	if ((!rst_ni))
-2-:	90	if (clr_i)
-3-:	92	if (rptr_wrap)
-4-:	94	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Not Covered
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	0	0.00
CONT_ASSIGN	29	1	0	0.00
CONT_ASSIGN	30	1	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	33	1	0	0.00
ALWAYS	76	7	0	0.00
ALWAYS	88	7	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	0	1
30	0	1
32	0	1
33	0	1
76	0	1
77	0	1
78	0	1
79		unreachable
80	0	1
81	0	1
82	0	1
83	0	1
			==> MISSING_ELSE
88	0	1
89	0	1
90	0	1
91		unreachable
92	0	1
93	0	1
94	0	1
95	0	1
			==> MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_to_prog_fifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	0	0.00
IF	76	4	0	0.00
IF	88	4	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	78	if (clr_i)
-3-:	80	if (wptr_wrap)
-4-:	82	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	88	if ((!rst_ni))
-2-:	90	if (clr_i)
-3-:	92	if (rptr_wrap)
-4-:	94	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		15	0	0.00
CONT_ASSIGN	29	1	0	0.00
CONT_ASSIGN	30	0	0
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	33	1	0	0.00
ALWAYS	76	7	0	0.00
ALWAYS	88	5	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	0	1
30		unreachable
32	0	1
33	0	1
76	0	1
77	0	1
78	0	1
79		unreachable
80	0	1
81	0	1
82	0	1
83	0	1
			==> MISSING_ELSE
88	0	1
89	0	1
90	0	1
91		unreachable
92	0	1
93		unreachable
94	0	1
95		unreachable
			==> MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_to_prog_fifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		6	0	0.00
IF	76	4	0	0.00
IF	88	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	78	if (clr_i)
-3-:	80	if (wptr_wrap)
-4-:	82	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	88	if ((!rst_ni))
-2-:	90	if (clr_i)
-3-:	92	if (rptr_wrap)
-4-:	94	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Unreachable
0	0	1	-	Unreachable
0	0	0	1	Unreachable
0	0	0	0	Not Covered

Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		15	0	0.00
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	33	1	0	0.00
ALWAYS	76	5	0	0.00
ALWAYS	88	7	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29		unreachable
30	0	1
32	0	1
33	0	1
76	0	1
77	0	1
78	0	1
79		unreachable
80	0	1
81		unreachable
82	0	1
83		unreachable
			==> MISSING_ELSE
88	0	1
89	0	1
90	0	1
91		unreachable
92	0	1
93	0	1
94	0	1
95	0	1
			==> MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_to_prog_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		6	0	0.00
IF	76	2	0	0.00
IF	88	4	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	78	if (clr_i)
-3-:	80	if (wptr_wrap)
-4-:	82	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Unreachable
0	0	1	-	Unreachable
0	0	0	1	Unreachable
0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	88	if ((!rst_ni))
-2-:	90	if (clr_i)
-3-:	92	if (rptr_wrap)
-4-:	94	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

Line Coverage for Instance : tb.dut.u_prog_fifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		20	0	0.00
CONT_ASSIGN	29	1	0	0.00
CONT_ASSIGN	30	1	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	33	1	0	0.00
ALWAYS	76	8	0	0.00
ALWAYS	88	8	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	0	1
30	0	1
32	0	1
33	0	1
76	0	1
77	0	1
78	0	1
79	0	1
80	0	1
81	0	1
82	0	1
83	0	1
			==> MISSING_ELSE
88	0	1
89	0	1
90	0	1
91	0	1
92	0	1
93	0	1
94	0	1
95	0	1
			==> MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_prog_fifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		10	0	0.00
IF	76	5	0	0.00
IF	88	5	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	78	if (clr_i)
-3-:	80	if (wptr_wrap)
-4-:	82	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Not Covered
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	88	if ((!rst_ni))
-2-:	90	if (clr_i)
-3-:	92	if (rptr_wrap)
-4-:	94	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Not Covered
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	0	0.00
CONT_ASSIGN	29	1	0	0.00
CONT_ASSIGN	30	1	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	33	1	0	0.00
ALWAYS	76	7	0	0.00
ALWAYS	88	7	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	0	1
30	0	1
32	0	1
33	0	1
76	0	1
77	0	1
78	0	1
79		unreachable
80	0	1
81	0	1
82	0	1
83	0	1
			==> MISSING_ELSE
88	0	1
89	0	1
90	0	1
91		unreachable
92	0	1
93	0	1
94	0	1
95	0	1
			==> MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_to_rd_fifo.u_reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	0	0.00
IF	76	4	0	0.00
IF	88	4	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	78	if (clr_i)
-3-:	80	if (wptr_wrap)
-4-:	82	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	88	if ((!rst_ni))
-2-:	90	if (clr_i)
-3-:	92	if (rptr_wrap)
-4-:	94	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	0	0.00
CONT_ASSIGN	29	1	0	0.00
CONT_ASSIGN	30	1	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	33	1	0	0.00
ALWAYS	76	7	0	0.00
ALWAYS	88	7	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	0	1
30	0	1
32	0	1
33	0	1
76	0	1
77	0	1
78	0	1
79		unreachable
80	0	1
81	0	1
82	0	1
83	0	1
			==> MISSING_ELSE
88	0	1
89	0	1
90	0	1
91		unreachable
92	0	1
93	0	1
94	0	1
95	0	1
			==> MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_to_rd_fifo.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	0	0.00
IF	76	4	0	0.00
IF	88	4	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	78	if (clr_i)
-3-:	80	if (wptr_wrap)
-4-:	82	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	88	if ((!rst_ni))
-2-:	90	if (clr_i)
-3-:	92	if (rptr_wrap)
-4-:	94	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		5	0	0.00
CONT_ASSIGN	29	1	0	0.00
CONT_ASSIGN	30	1	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	33	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	0	1
30	0	1
32	0	1
33	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.u_fifo_cnt

	Total	Covered	Percent
Conditions	3	0	0.00
Logical	3	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       72
 EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
             ------------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

Line Coverage for Instance : tb.dut.u_sw_rd_fifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		20	0	0.00
CONT_ASSIGN	29	1	0	0.00
CONT_ASSIGN	30	1	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	33	1	0	0.00
ALWAYS	76	8	0	0.00
ALWAYS	88	8	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	0	1
30	0	1
32	0	1
33	0	1
76	0	1
77	0	1
78	0	1
79	0	1
80	0	1
81	0	1
82	0	1
83	0	1
			==> MISSING_ELSE
88	0	1
89	0	1
90	0	1
91	0	1
92	0	1
93	0	1
94	0	1
95	0	1
			==> MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_sw_rd_fifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		10	0	0.00
IF	76	5	0	0.00
IF	88	5	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	78	if (clr_i)
-3-:	80	if (wptr_wrap)
-4-:	82	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Not Covered
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	88	if ((!rst_ni))
-2-:	90	if (clr_i)
-3-:	92	if (rptr_wrap)
-4-:	94	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Not Covered
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	0	0.00
CONT_ASSIGN	29	1	0	0.00
CONT_ASSIGN	30	1	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	33	1	0	0.00
ALWAYS	76	7	0	0.00
ALWAYS	88	7	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	0	1
30	0	1
32	0	1
33	0	1
76	0	1
77	0	1
78	0	1
79		unreachable
80	0	1
81	0	1
82	0	1
83	0	1
			==> MISSING_ELSE
88	0	1
89	0	1
90	0	1
91		unreachable
92	0	1
93	0	1
94	0	1
95	0	1
			==> MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_reqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	0	0.00
IF	76	4	0	0.00
IF	88	4	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	78	if (clr_i)
-3-:	80	if (wptr_wrap)
-4-:	82	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	88	if ((!rst_ni))
-2-:	90	if (clr_i)
-3-:	92	if (rptr_wrap)
-4-:	94	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	0	0.00
CONT_ASSIGN	29	1	0	0.00
CONT_ASSIGN	30	1	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	33	1	0	0.00
ALWAYS	76	7	0	0.00
ALWAYS	88	7	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	0	1
30	0	1
32	0	1
33	0	1
76	0	1
77	0	1
78	0	1
79		unreachable
80	0	1
81	0	1
82	0	1
83	0	1
			==> MISSING_ELSE
88	0	1
89	0	1
90	0	1
91		unreachable
92	0	1
93	0	1
94	0	1
95	0	1
			==> MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	0	0.00
IF	76	4	0	0.00
IF	88	4	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	78	if (clr_i)
-3-:	80	if (wptr_wrap)
-4-:	82	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	88	if ((!rst_ni))
-2-:	90	if (clr_i)
-3-:	92	if (rptr_wrap)
-4-:	94	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	0	0.00
CONT_ASSIGN	29	1	0	0.00
CONT_ASSIGN	30	1	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	33	1	0	0.00
ALWAYS	76	7	0	0.00
ALWAYS	88	7	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	0	1
30	0	1
32	0	1
33	0	1
76	0	1
77	0	1
78	0	1
79		unreachable
80	0	1
81	0	1
82	0	1
83	0	1
			==> MISSING_ELSE
88	0	1
89	0	1
90	0	1
91		unreachable
92	0	1
93	0	1
94	0	1
95	0	1
			==> MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rspfifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	0	0.00
IF	76	4	0	0.00
IF	88	4	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	78	if (clr_i)
-3-:	80	if (wptr_wrap)
-4-:	82	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	88	if ((!rst_ni))
-2-:	90	if (clr_i)
-3-:	92	if (rptr_wrap)
-4-:	94	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

Line Coverage for Instance : tb.dut.u_eflash.u_bank_sequence_fifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	0	0.00
CONT_ASSIGN	29	1	0	0.00
CONT_ASSIGN	30	1	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	33	1	0	0.00
ALWAYS	76	7	0	0.00
ALWAYS	88	7	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	0	1
30	0	1
32	0	1
33	0	1
76	0	1
77	0	1
78	0	1
79		unreachable
80	0	1
81	0	1
82	0	1
83	0	1
			==> MISSING_ELSE
88	0	1
89	0	1
90	0	1
91		unreachable
92	0	1
93	0	1
94	0	1
95	0	1
			==> MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.u_bank_sequence_fifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	0	0.00
IF	76	4	0	0.00
IF	88	4	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	78	if (clr_i)
-3-:	80	if (wptr_wrap)
-4-:	82	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	88	if ((!rst_ni))
-2-:	90	if (clr_i)
-3-:	92	if (rptr_wrap)
-4-:	94	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	0	0.00
CONT_ASSIGN	29	1	0	0.00
CONT_ASSIGN	30	1	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	33	1	0	0.00
ALWAYS	76	7	0	0.00
ALWAYS	88	7	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	0	1
30	0	1
32	0	1
33	0	1
76	0	1
77	0	1
78	0	1
79		unreachable
80	0	1
81	0	1
82	0	1
83	0	1
			==> MISSING_ELSE
88	0	1
89	0	1
90	0	1
91		unreachable
92	0	1
93	0	1
94	0	1
95	0	1
			==> MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	0	0.00
IF	76	4	0	0.00
IF	88	4	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	78	if (clr_i)
-3-:	80	if (wptr_wrap)
-4-:	82	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	88	if ((!rst_ni))
-2-:	90	if (clr_i)
-3-:	92	if (rptr_wrap)
-4-:	94	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		18	0	0.00
CONT_ASSIGN	29	1	0	0.00
CONT_ASSIGN	30	1	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	33	1	0	0.00
ALWAYS	76	7	0	0.00
ALWAYS	88	7	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	0	1
30	0	1
32	0	1
33	0	1
76	0	1
77	0	1
78	0	1
79		unreachable
80	0	1
81	0	1
82	0	1
83	0	1
			==> MISSING_ELSE
88	0	1
89	0	1
90	0	1
91		unreachable
92	0	1
93	0	1
94	0	1
95	0	1
			==> MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		8	0	0.00
IF	76	4	0	0.00
IF	88	4	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	78	if (clr_i)
-3-:	80	if (wptr_wrap)
-4-:	82	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	88	if ((!rst_ni))
-2-:	90	if (clr_i)
-3-:	92	if (rptr_wrap)
-4-:	94	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		5	0	0.00
CONT_ASSIGN	29	1	0	0.00
CONT_ASSIGN	30	1	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	33	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	0	1
30	0	1
32	0	1
33	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt

	Total	Covered	Percent
Conditions	3	0	0.00
Logical	3	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       72
 EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
             ------------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		5	0	0.00
CONT_ASSIGN	29	1	0	0.00
CONT_ASSIGN	30	1	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	33	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	0	1
30	0	1
32	0	1
33	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt

	Total	Covered	Percent
Conditions	3	0	0.00
Logical	3	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       72
 EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
             ------------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		5	0	0.00
CONT_ASSIGN	29	1	0	0.00
CONT_ASSIGN	30	1	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	33	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	0	1
30	0	1
32	0	1
33	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt

	Total	Covered	Percent
Conditions	3	0	0.00
Logical	3	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       72
 EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
             ------------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		15	0	0.00
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	33	1	0	0.00
ALWAYS	76	5	0	0.00
ALWAYS	88	7	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29		unreachable
30	0	1
32	0	1
33	0	1
76	0	1
77	0	1
78	0	1
79		unreachable
80	0	1
81		unreachable
82	0	1
83		unreachable
			==> MISSING_ELSE
88	0	1
89	0	1
90	0	1
91		unreachable
92	0	1
93	0	1
94	0	1
95	0	1
			==> MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		6	0	0.00
IF	76	2	0	0.00
IF	88	4	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	78	if (clr_i)
-3-:	80	if (wptr_wrap)
-4-:	82	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Unreachable
0	0	1	-	Unreachable
0	0	0	1	Unreachable
0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	88	if ((!rst_ni))
-2-:	90	if (clr_i)
-3-:	92	if (rptr_wrap)
-4-:	94	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		5	0	0.00
CONT_ASSIGN	29	1	0	0.00
CONT_ASSIGN	30	1	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	33	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	0	1
30	0	1
32	0	1
33	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.u_fifo_cnt

	Total	Covered	Percent
Conditions	3	0	0.00
Logical	3	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       72
 EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
             ------------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		5	0	0.00
CONT_ASSIGN	29	1	0	0.00
CONT_ASSIGN	30	1	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	33	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	0	1
30	0	1
32	0	1
33	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.u_fifo_cnt

	Total	Covered	Percent
Conditions	3	0	0.00
Logical	3	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       72
 EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
             ------------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		5	0	0.00
CONT_ASSIGN	29	1	0	0.00
CONT_ASSIGN	30	1	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	33	1	0	0.00
CONT_ASSIGN	72	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29	0	1
30	0	1
32	0	1
33	0	1
72	0	1

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.u_fifo_cnt

	Total	Covered	Percent
Conditions	3	0	0.00
Logical	3	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       72
 EXPRESSION (gen_secure_ptrs.wptr_err | gen_secure_ptrs.rptr_err)
             ------------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
TOTAL		15	0	0.00
CONT_ASSIGN	29	0	0
CONT_ASSIGN	30	1	0	0.00
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	33	1	0	0.00
ALWAYS	76	5	0	0.00
ALWAYS	88	7	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
29		unreachable
30	0	1
32	0	1
33	0	1
76	0	1
77	0	1
78	0	1
79		unreachable
80	0	1
81		unreachable
82	0	1
83		unreachable
			==> MISSING_ELSE
88	0	1
89	0	1
90	0	1
91		unreachable
92	0	1
93	0	1
94	0	1
95	0	1
			==> MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.gen_normal_fifo.u_fifo_cnt

	Line No.	Total	Covered	Percent
Branches		6	0	0.00
IF	76	2	0	0.00
IF	88	4	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	if ((!rst_ni))
-2-:	78	if (clr_i)
-3-:	80	if (wptr_wrap)
-4-:	82	if (incr_wptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Unreachable
0	0	1	-	Unreachable
0	0	0	1	Unreachable
0	0	0	0	Not Covered

	LineNo.	Expression
-1-:	88	if ((!rst_ni))
-2-:	90	if (clr_i)
-3-:	92	if (rptr_wrap)
-4-:	94	if (incr_rptr_i)

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Not Covered
0	1	-	-	Unreachable
0	0	1	-	Not Covered
0	0	0	1	Not Covered
0	0	0	0	Not Covered