Unified Coverage Report :: Module Instance :: tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2308514	644490	0	0
DepthKnown_A	2308514	2228562	0	0
RvalidKnown_A	2308514	2228562	0	0
WreadyKnown_A	2308514	2228562	0	0
gen_passthru_fifo.paramCheckPass	215	215	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	644490	0	0
T1	1226	142	0	0
T2	1444	142	0	0
T3	1063	103	0	0
T4	16375	8533	0	0
T5	33267	17349	0	0
T7	1257	124	0	0
T9	1435	142	0	0
T11	2679	1090	0	0
T12	5117	2765	0	0
T13	973	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2228562	0	0
T1	1226	1131	0	0
T2	1444	1384	0	0
T3	1063	983	0	0
T4	16375	13949	0	0
T5	33267	28763	0	0
T7	1257	1186	0	0
T9	1435	1374	0	0
T11	2679	2599	0	0
T12	5117	5065	0	0
T13	973	884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2228562	0	0
T1	1226	1131	0	0
T2	1444	1384	0	0
T3	1063	983	0	0
T4	16375	13949	0	0
T5	33267	28763	0	0
T7	1257	1186	0	0
T9	1435	1374	0	0
T11	2679	2599	0	0
T12	5117	5065	0	0
T13	973	884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2228562	0	0
T1	1226	1131	0	0
T2	1444	1384	0	0
T3	1063	983	0	0
T4	16375	13949	0	0
T5	33267	28763	0	0
T7	1257	1186	0	0
T9	1435	1374	0	0
T11	2679	2599	0	0
T12	5117	5065	0	0
T13	973	884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2308514	661396	0	0
DepthKnown_A	2308514	2228562	0	0
RvalidKnown_A	2308514	2228562	0	0
WreadyKnown_A	2308514	2228562	0	0
gen_passthru_fifo.paramCheckPass	215	215	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	661396	0	0
T1	1226	142	0	0
T2	1444	142	0	0
T3	1063	103	0	0
T4	16375	5160	0	0
T5	33267	10433	0	0
T7	1257	124	0	0
T9	1435	142	0	0
T11	2679	597	0	0
T12	5117	1435	0	0
T13	973	57	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2228562	0	0
T1	1226	1131	0	0
T2	1444	1384	0	0
T3	1063	983	0	0
T4	16375	13949	0	0
T5	33267	28763	0	0
T7	1257	1186	0	0
T9	1435	1374	0	0
T11	2679	2599	0	0
T12	5117	5065	0	0
T13	973	884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2228562	0	0
T1	1226	1131	0	0
T2	1444	1384	0	0
T3	1063	983	0	0
T4	16375	13949	0	0
T5	33267	28763	0	0
T7	1257	1186	0	0
T9	1435	1374	0	0
T11	2679	2599	0	0
T12	5117	5065	0	0
T13	973	884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2228562	0	0
T1	1226	1131	0	0
T2	1444	1384	0	0
T3	1063	983	0	0
T4	16375	13949	0	0
T5	33267	28763	0	0
T7	1257	1186	0	0
T9	1435	1374	0	0
T11	2679	2599	0	0
T12	5117	5065	0	0
T13	973	884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2308514	8818	0	0
DepthKnown_A	2308514	2228562	0	0
RvalidKnown_A	2308514	2228562	0	0
WreadyKnown_A	2308514	2228562	0	0
gen_passthru_fifo.paramCheckPass	215	215	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	8818	0	0
T4	16375	0	0	0
T5	33267	0	0	0
T6	17313	0	0	0
T7	1257	0	0	0
T8	1226	0	0	0
T9	1435	0	0	0
T10	5738	0	0	0
T11	2679	62	0	0
T12	5117	259	0	0
T14	4803	517	0	0
T15	0	228	0	0
T16	0	85	0	0
T17	0	102	0	0
T18	0	200	0	0
T19	0	55	0	0
T20	0	49	0	0
T21	0	93	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2228562	0	0
T1	1226	1131	0	0
T2	1444	1384	0	0
T3	1063	983	0	0
T4	16375	13949	0	0
T5	33267	28763	0	0
T7	1257	1186	0	0
T9	1435	1374	0	0
T11	2679	2599	0	0
T12	5117	5065	0	0
T13	973	884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2228562	0	0
T1	1226	1131	0	0
T2	1444	1384	0	0
T3	1063	983	0	0
T4	16375	13949	0	0
T5	33267	28763	0	0
T7	1257	1186	0	0
T9	1435	1374	0	0
T11	2679	2599	0	0
T12	5117	5065	0	0
T13	973	884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2228562	0	0
T1	1226	1131	0	0
T2	1444	1384	0	0
T3	1063	983	0	0
T4	16375	13949	0	0
T5	33267	28763	0	0
T7	1257	1186	0	0
T9	1435	1374	0	0
T11	2679	2599	0	0
T12	5117	5065	0	0
T13	973	884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2308514	7731	0	0
DepthKnown_A	2308514	2228562	0	0
RvalidKnown_A	2308514	2228562	0	0
WreadyKnown_A	2308514	2228562	0	0
gen_passthru_fifo.paramCheckPass	215	215	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	7731	0	0
T4	16375	0	0	0
T5	33267	0	0	0
T6	17313	0	0	0
T7	1257	0	0	0
T8	1226	0	0	0
T9	1435	0	0	0
T10	5738	0	0	0
T11	2679	61	0	0
T12	5117	214	0	0
T14	4803	412	0	0
T15	0	218	0	0
T16	0	82	0	0
T17	0	96	0	0
T18	0	109	0	0
T19	0	52	0	0
T20	0	49	0	0
T21	0	47	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2228562	0	0
T1	1226	1131	0	0
T2	1444	1384	0	0
T3	1063	983	0	0
T4	16375	13949	0	0
T5	33267	28763	0	0
T7	1257	1186	0	0
T9	1435	1374	0	0
T11	2679	2599	0	0
T12	5117	5065	0	0
T13	973	884	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2228562	0	0
T1	1226	1131	0	0
T2	1444	1384	0	0
T3	1063	983	0	0
T4	16375	13949	0	0
T5	33267	28763	0	0
T7	1257	1186	0	0
T9	1435	1374	0	0
T11	2679	2599	0	0
T12	5117	5065	0	0
T13	973	884	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2228562	0	0
T1	1226	1131	0	0
T2	1444	1384	0	0
T3	1063	983	0	0
T4	16375	13949	0	0
T5	33267	28763	0	0
T7	1257	1186	0	0
T9	1435	1374	0	0
T11	2679	2599	0	0
T12	5117	5065	0	0
T13	973	884	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	215	215	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T7	1	1	0	0
T9	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0