Unified Coverage Report :: Module :: flash_ctrl_core_csr_assert_fpv

Module : flash_ctrl_core_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_flash_ctrl_csr_assert_0/flash_ctrl_core_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.flash_ctrl_core_csr_assert	100.00						100.00

---

Module Instance : tb.dut.flash_ctrl_core_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
16.65	0.00	0.00	66.62		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : flash_ctrl_core_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	87	87	100.00	87	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	87	87	100.00	87	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2308514	5014	0	0
addr_rd_A	2308514	1134	0	0
bank0_info0_page_cfg_0_rd_A	2308514	2699	0	0
bank0_info0_page_cfg_1_rd_A	2308514	1688	0	0
bank0_info0_page_cfg_2_rd_A	2308514	2560	0	0
bank0_info0_page_cfg_3_rd_A	2308514	2009	0	0
bank0_info0_page_cfg_4_rd_A	2308514	2562	0	0
bank0_info0_page_cfg_5_rd_A	2308514	2766	0	0
bank0_info0_page_cfg_6_rd_A	2308514	2093	0	0
bank0_info0_page_cfg_7_rd_A	2308514	1959	0	0
bank0_info0_page_cfg_8_rd_A	2308514	2498	0	0
bank0_info0_page_cfg_9_rd_A	2308514	2440	0	0
bank0_info0_regwen_0_rd_A	2308514	1473	0	0
bank0_info0_regwen_1_rd_A	2308514	1467	0	0
bank0_info0_regwen_2_rd_A	2308514	1786	0	0
bank0_info0_regwen_3_rd_A	2308514	1291	0	0
bank0_info0_regwen_4_rd_A	2308514	1657	0	0
bank0_info0_regwen_5_rd_A	2308514	1729	0	0
bank0_info0_regwen_6_rd_A	2308514	753	0	0
bank0_info0_regwen_7_rd_A	2308514	1289	0	0
bank0_info0_regwen_8_rd_A	2308514	1191	0	0
bank0_info0_regwen_9_rd_A	2308514	1535	0	0
bank0_info1_page_cfg_rd_A	2308514	2596	0	0
bank0_info1_regwen_rd_A	2308514	1272	0	0
bank0_info2_page_cfg_0_rd_A	2308514	1888	0	0
bank0_info2_page_cfg_1_rd_A	2308514	2112	0	0
bank0_info2_regwen_0_rd_A	2308514	1723	0	0
bank0_info2_regwen_1_rd_A	2308514	1626	0	0
bank1_info0_page_cfg_0_rd_A	2308514	2402	0	0
bank1_info0_page_cfg_1_rd_A	2308514	2113	0	0
bank1_info0_page_cfg_2_rd_A	2308514	2114	0	0
bank1_info0_page_cfg_3_rd_A	2308514	2366	0	0
bank1_info0_page_cfg_4_rd_A	2308514	2458	0	0
bank1_info0_page_cfg_5_rd_A	2308514	1816	0	0
bank1_info0_page_cfg_6_rd_A	2308514	2465	0	0
bank1_info0_page_cfg_7_rd_A	2308514	2594	0	0
bank1_info0_page_cfg_8_rd_A	2308514	2640	0	0
bank1_info0_page_cfg_9_rd_A	2308514	1626	0	0
bank1_info0_regwen_0_rd_A	2308514	1644	0	0
bank1_info0_regwen_1_rd_A	2308514	1720	0	0
bank1_info0_regwen_2_rd_A	2308514	1232	0	0
bank1_info0_regwen_3_rd_A	2308514	1740	0	0
bank1_info0_regwen_4_rd_A	2308514	1295	0	0
bank1_info0_regwen_5_rd_A	2308514	1287	0	0
bank1_info0_regwen_6_rd_A	2308514	1707	0	0
bank1_info0_regwen_7_rd_A	2308514	1202	0	0
bank1_info0_regwen_8_rd_A	2308514	950	0	0
bank1_info0_regwen_9_rd_A	2308514	1340	0	0
bank1_info1_page_cfg_rd_A	2308514	2453	0	0
bank1_info1_regwen_rd_A	2308514	1002	0	0
bank1_info2_page_cfg_0_rd_A	2308514	2466	0	0
bank1_info2_page_cfg_1_rd_A	2308514	1609	0	0
bank1_info2_regwen_0_rd_A	2308514	937	0	0
bank1_info2_regwen_1_rd_A	2308514	1740	0	0
bank_cfg_regwen_rd_A	2308514	1742	0	0
default_region_rd_A	2308514	1870	0	0
exec_rd_A	2308514	1972	0	0
fifo_lvl_rd_A	2308514	1894	0	0
fifo_rst_rd_A	2308514	1859	0	0
hw_info_cfg_override_rd_A	2308514	1843	0	0
intr_enable_rd_A	2308514	1548	0	0
mp_region_0_rd_A	2308514	1952	0	0
mp_region_1_rd_A	2308514	1378	0	0
mp_region_2_rd_A	2308514	1776	0	0
mp_region_3_rd_A	2308514	1689	0	0
mp_region_4_rd_A	2308514	1897	0	0
mp_region_5_rd_A	2308514	1485	0	0
mp_region_6_rd_A	2308514	1352	0	0
mp_region_7_rd_A	2308514	1428	0	0
mp_region_cfg_0_rd_A	2308514	2292	0	0
mp_region_cfg_1_rd_A	2308514	2179	0	0
mp_region_cfg_2_rd_A	2308514	1792	0	0
mp_region_cfg_3_rd_A	2308514	2710	0	0
mp_region_cfg_4_rd_A	2308514	2792	0	0
mp_region_cfg_5_rd_A	2308514	2615	0	0
mp_region_cfg_6_rd_A	2308514	2361	0	0
mp_region_cfg_7_rd_A	2308514	2552	0	0
phy_alert_cfg_rd_A	2308514	1419	0	0
region_cfg_regwen_0_rd_A	2308514	1776	0	0
region_cfg_regwen_1_rd_A	2308514	1678	0	0
region_cfg_regwen_2_rd_A	2308514	1164	0	0
region_cfg_regwen_3_rd_A	2308514	1782	0	0
region_cfg_regwen_4_rd_A	2308514	1748	0	0
region_cfg_regwen_5_rd_A	2308514	467	0	0
region_cfg_regwen_6_rd_A	2308514	1548	0	0
region_cfg_regwen_7_rd_A	2308514	1273	0	0
scratch_rd_A	2308514	1675	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	5014	0	0
T4	16375	0	0	0
T5	33267	0	0	0
T6	17313	0	0	0
T7	1257	0	0	0
T8	1226	0	0	0
T9	1435	0	0	0
T10	5738	0	0	0
T11	2679	144	0	0
T12	5117	141	0	0
T14	4803	185	0	0
T15	0	338	0	0
T17	0	4	0	0
T18	0	69	0	0
T19	0	3	0	0
T20	0	4	0	0
T22	0	223	0	0
T23	0	1	0	0

addr_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1134	0	0
T30	4892	0	0	0
T31	6278	8	0	0
T32	7655	0	0	0
T33	0	25	0	0
T37	0	1	0	0
T49	10569	0	0	0
T50	0	4	0	0
T51	0	26	0	0
T53	74737	264	0	0
T54	32063	0	0	0
T57	0	27	0	0
T61	0	38	0	0
T69	0	2	0	0
T70	0	53	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank0_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2699	0	0
T30	4892	0	0	0
T31	6278	35	0	0
T32	7655	0	0	0
T33	0	9	0	0
T49	10569	17	0	0
T50	0	39	0	0
T51	0	20	0	0
T53	74737	281	0	0
T54	32063	0	0	0
T57	0	113	0	0
T69	0	6	0	0
T70	0	171	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0
T75	0	3	0	0

bank0_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1688	0	0
T30	4892	3	0	0
T31	6278	29	0	0
T32	7655	0	0	0
T33	0	21	0	0
T37	0	8	0	0
T38	0	4	0	0
T49	10569	42	0	0
T50	0	20	0	0
T51	0	7	0	0
T53	74737	244	0	0
T54	32063	0	0	0
T69	0	47	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank0_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2560	0	0
T30	4892	4	0	0
T31	6278	6	0	0
T32	7655	0	0	0
T33	0	24	0	0
T49	10569	1	0	0
T50	0	30	0	0
T51	0	3	0	0
T53	74737	257	0	0
T54	32063	0	0	0
T57	0	82	0	0
T69	0	37	0	0
T70	0	74	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank0_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2009	0	0
T30	4892	0	0	0
T31	6278	34	0	0
T32	7655	0	0	0
T33	0	5	0	0
T37	0	3	0	0
T38	0	4	0	0
T49	10569	25	0	0
T51	0	6	0	0
T53	74737	269	0	0
T54	32063	0	0	0
T57	0	104	0	0
T69	0	33	0	0
T70	0	127	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank0_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2562	0	0
T30	4892	7	0	0
T31	6278	2	0	0
T32	7655	0	0	0
T33	0	33	0	0
T49	10569	44	0	0
T50	0	15	0	0
T51	0	17	0	0
T53	74737	312	0	0
T54	32063	0	0	0
T57	0	85	0	0
T69	0	4	0	0
T70	0	129	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank0_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2766	0	0
T30	4892	2	0	0
T31	6278	60	0	0
T32	7655	0	0	0
T33	0	31	0	0
T37	0	5	0	0
T38	0	7	0	0
T49	10569	36	0	0
T50	0	52	0	0
T51	0	39	0	0
T53	74737	270	0	0
T54	32063	0	0	0
T69	0	3	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank0_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2093	0	0
T30	4892	0	0	0
T31	6278	16	0	0
T32	7655	0	0	0
T33	0	54	0	0
T37	0	7	0	0
T38	0	1	0	0
T49	10569	26	0	0
T50	0	43	0	0
T51	0	8	0	0
T53	74737	271	0	0
T54	32063	0	0	0
T69	0	22	0	0
T70	0	170	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank0_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1959	0	0
T30	4892	5	0	0
T31	6278	34	0	0
T32	7655	0	0	0
T33	0	16	0	0
T37	0	2	0	0
T49	10569	55	0	0
T50	0	18	0	0
T51	0	26	0	0
T53	74737	246	0	0
T54	32063	0	0	0
T69	0	28	0	0
T70	0	163	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank0_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2498	0	0
T30	4892	2	0	0
T31	6278	38	0	0
T32	7655	0	0	0
T33	0	23	0	0
T37	0	14	0	0
T49	10569	26	0	0
T51	0	42	0	0
T53	74737	219	0	0
T54	32063	0	0	0
T57	0	83	0	0
T69	0	27	0	0
T70	0	141	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank0_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2440	0	0
T30	4892	4	0	0
T31	6278	35	0	0
T32	7655	0	0	0
T33	0	26	0	0
T37	0	8	0	0
T49	10569	35	0	0
T50	0	18	0	0
T51	0	16	0	0
T54	32063	0	0	0
T57	0	97	0	0
T69	0	27	0	0
T70	0	127	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0
T76	1509	0	0	0
T77	807	0	0	0

bank0_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1473	0	0
T30	4892	5	0	0
T31	6278	3	0	0
T32	7655	0	0	0
T33	0	24	0	0
T38	0	8	0	0
T49	10569	8	0	0
T50	0	5	0	0
T51	0	8	0	0
T54	32063	0	0	0
T57	0	22	0	0
T69	0	1	0	0
T70	0	52	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0
T76	1509	0	0	0
T77	807	0	0	0

bank0_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1467	0	0
T17	4327	0	0	0
T31	6278	2	0	0
T32	7655	0	0	0
T33	0	22	0	0
T37	0	3	0	0
T49	10569	11	0	0
T50	0	3	0	0
T51	0	36	0	0
T57	0	16	0	0
T69	0	8	0	0
T70	0	25	0	0
T74	1107	0	0	0
T75	0	7	0	0
T76	1509	0	0	0
T77	807	0	0	0
T78	915	0	0	0
T79	1436	0	0	0
T80	720	0	0	0

bank0_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1786	0	0
T30	4892	5	0	0
T31	6278	5	0	0
T32	7655	0	0	0
T33	0	29	0	0
T38	0	6	0	0
T49	10569	26	0	0
T50	0	25	0	0
T51	0	20	0	0
T53	74737	311	0	0
T54	32063	0	0	0
T69	0	10	0	0
T70	0	33	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank0_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1291	0	0
T30	4892	2	0	0
T31	6278	8	0	0
T32	7655	0	0	0
T33	0	18	0	0
T37	0	3	0	0
T38	0	6	0	0
T49	10569	19	0	0
T50	0	12	0	0
T51	0	33	0	0
T53	74737	271	0	0
T54	32063	0	0	0
T69	0	2	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank0_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1657	0	0
T30	4892	5	0	0
T31	6278	7	0	0
T32	7655	0	0	0
T33	0	3	0	0
T49	10569	11	0	0
T50	0	30	0	0
T51	0	59	0	0
T53	74737	254	0	0
T54	32063	0	0	0
T57	0	5	0	0
T69	0	2	0	0
T70	0	43	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank0_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1729	0	0
T30	4892	5	0	0
T31	6278	14	0	0
T32	7655	0	0	0
T33	0	9	0	0
T37	0	4	0	0
T38	0	4	0	0
T49	10569	36	0	0
T50	0	5	0	0
T51	0	76	0	0
T53	74737	293	0	0
T54	32063	0	0	0
T69	0	4	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank0_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	753	0	0
T30	4892	3	0	0
T31	6278	14	0	0
T32	7655	0	0	0
T33	0	6	0	0
T37	0	6	0	0
T49	10569	31	0	0
T50	0	6	0	0
T51	0	26	0	0
T53	74737	305	0	0
T54	32063	0	0	0
T69	0	6	0	0
T70	0	37	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank0_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1289	0	0
T30	4892	5	0	0
T31	6278	5	0	0
T32	7655	0	0	0
T33	0	6	0	0
T37	0	5	0	0
T49	10569	6	0	0
T50	0	23	0	0
T51	0	47	0	0
T53	74737	315	0	0
T54	32063	0	0	0
T57	0	12	0	0
T70	0	34	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank0_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1191	0	0
T30	4892	8	0	0
T31	6278	14	0	0
T32	7655	0	0	0
T33	0	54	0	0
T37	0	1	0	0
T49	10569	39	0	0
T50	0	25	0	0
T51	0	3	0	0
T53	74737	235	0	0
T54	32063	0	0	0
T69	0	8	0	0
T70	0	35	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank0_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1535	0	0
T30	4892	6	0	0
T31	6278	9	0	0
T32	7655	0	0	0
T33	0	20	0	0
T49	10569	19	0	0
T50	0	12	0	0
T51	0	21	0	0
T53	74737	231	0	0
T54	32063	0	0	0
T57	0	11	0	0
T70	0	48	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0
T75	0	2	0	0

bank0_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2596	0	0
T30	4892	1	0	0
T31	6278	38	0	0
T32	7655	0	0	0
T33	0	7	0	0
T37	0	6	0	0
T49	10569	54	0	0
T50	0	18	0	0
T51	0	18	0	0
T53	74737	316	0	0
T54	32063	0	0	0
T57	0	118	0	0
T70	0	140	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank0_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1272	0	0
T30	4892	3	0	0
T31	6278	14	0	0
T32	7655	0	0	0
T33	0	51	0	0
T38	0	4	0	0
T49	10569	48	0	0
T51	0	55	0	0
T53	74737	249	0	0
T54	32063	0	0	0
T57	0	34	0	0
T69	0	8	0	0
T70	0	44	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank0_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1888	0	0
T30	4892	1	0	0
T31	6278	42	0	0
T32	7655	0	0	0
T33	0	33	0	0
T37	0	10	0	0
T38	0	3	0	0
T49	10569	7	0	0
T50	0	27	0	0
T51	0	25	0	0
T54	32063	0	0	0
T69	0	42	0	0
T70	0	170	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0
T76	1509	0	0	0
T77	807	0	0	0

bank0_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2112	0	0
T30	4892	0	0	0
T31	6278	41	0	0
T32	7655	0	0	0
T33	0	36	0	0
T38	0	4	0	0
T49	10569	5	0	0
T50	0	28	0	0
T51	0	12	0	0
T53	74737	289	0	0
T54	32063	0	0	0
T57	0	105	0	0
T69	0	7	0	0
T70	0	114	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank0_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1723	0	0
T30	4892	7	0	0
T31	6278	10	0	0
T32	7655	0	0	0
T33	0	14	0	0
T37	0	5	0	0
T38	0	2	0	0
T49	10569	42	0	0
T50	0	26	0	0
T51	0	37	0	0
T53	74737	272	0	0
T54	32063	0	0	0
T69	0	17	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank0_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1626	0	0
T30	4892	0	0	0
T31	6278	6	0	0
T32	7655	0	0	0
T33	0	1	0	0
T37	0	4	0	0
T49	10569	27	0	0
T50	0	22	0	0
T51	0	1	0	0
T53	74737	280	0	0
T54	32063	0	0	0
T57	0	12	0	0
T69	0	11	0	0
T70	0	31	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank1_info0_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2402	0	0
T30	4892	7	0	0
T31	6278	2	0	0
T32	7655	0	0	0
T33	0	22	0	0
T37	0	11	0	0
T49	10569	6	0	0
T50	0	32	0	0
T51	0	9	0	0
T53	74737	274	0	0
T54	32063	0	0	0
T69	0	25	0	0
T70	0	114	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank1_info0_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2113	0	0
T30	4892	3	0	0
T31	6278	32	0	0
T32	7655	0	0	0
T33	0	11	0	0
T37	0	9	0	0
T49	10569	3	0	0
T50	0	53	0	0
T51	0	15	0	0
T53	74737	269	0	0
T54	32063	0	0	0
T69	0	23	0	0
T70	0	173	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank1_info0_page_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2114	0	0
T30	4892	5	0	0
T31	6278	8	0	0
T32	7655	0	0	0
T33	0	5	0	0
T37	0	10	0	0
T49	10569	20	0	0
T50	0	26	0	0
T51	0	30	0	0
T53	74737	265	0	0
T54	32063	0	0	0
T69	0	37	0	0
T70	0	144	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank1_info0_page_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2366	0	0
T30	4892	3	0	0
T31	6278	43	0	0
T32	7655	0	0	0
T33	0	8	0	0
T37	0	15	0	0
T38	0	8	0	0
T49	10569	15	0	0
T50	0	14	0	0
T51	0	11	0	0
T54	32063	0	0	0
T69	0	3	0	0
T70	0	135	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0
T76	1509	0	0	0
T77	807	0	0	0

bank1_info0_page_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2458	0	0
T30	4892	6	0	0
T31	6278	25	0	0
T32	7655	0	0	0
T33	0	37	0	0
T49	10569	9	0	0
T50	0	38	0	0
T51	0	36	0	0
T54	32063	0	0	0
T57	0	94	0	0
T69	0	19	0	0
T70	0	112	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0
T75	0	24	0	0
T76	1509	0	0	0
T77	807	0	0	0

bank1_info0_page_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1816	0	0
T30	4892	1	0	0
T31	6278	28	0	0
T32	7655	0	0	0
T33	0	17	0	0
T37	0	5	0	0
T38	0	3	0	0
T49	10569	13	0	0
T50	0	56	0	0
T51	0	23	0	0
T53	74737	248	0	0
T54	32063	0	0	0
T69	0	22	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank1_info0_page_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2465	0	0
T30	4892	10	0	0
T31	6278	38	0	0
T32	7655	0	0	0
T33	0	13	0	0
T49	10569	38	0	0
T50	0	7	0	0
T51	0	9	0	0
T53	74737	311	0	0
T54	32063	0	0	0
T57	0	32	0	0
T69	0	38	0	0
T70	0	58	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank1_info0_page_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2594	0	0
T30	4892	1	0	0
T31	6278	6	0	0
T32	7655	0	0	0
T33	0	11	0	0
T37	0	2	0	0
T38	0	1	0	0
T49	10569	14	0	0
T50	0	24	0	0
T51	0	5	0	0
T53	74737	225	0	0
T54	32063	0	0	0
T69	0	24	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank1_info0_page_cfg_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2640	0	0
T30	4892	3	0	0
T31	6278	49	0	0
T32	7655	0	0	0
T33	0	4	0	0
T49	10569	9	0	0
T50	0	15	0	0
T51	0	32	0	0
T53	74737	208	0	0
T54	32063	0	0	0
T57	0	101	0	0
T69	0	11	0	0
T70	0	144	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank1_info0_page_cfg_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1626	0	0
T30	4892	9	0	0
T31	6278	43	0	0
T32	7655	0	0	0
T33	0	33	0	0
T37	0	1	0	0
T49	10569	0	0	0
T50	0	21	0	0
T51	0	14	0	0
T53	74737	280	0	0
T54	32063	0	0	0
T57	0	124	0	0
T69	0	38	0	0
T70	0	207	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank1_info0_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1644	0	0
T30	4892	9	0	0
T31	6278	6	0	0
T32	7655	0	0	0
T33	0	20	0	0
T37	0	1	0	0
T38	0	2	0	0
T49	10569	12	0	0
T50	0	22	0	0
T51	0	25	0	0
T53	74737	255	0	0
T54	32063	0	0	0
T69	0	11	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank1_info0_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1720	0	0
T30	4892	3	0	0
T31	6278	17	0	0
T32	7655	0	0	0
T33	0	38	0	0
T38	0	3	0	0
T49	10569	9	0	0
T50	0	10	0	0
T51	0	28	0	0
T53	74737	297	0	0
T54	32063	0	0	0
T69	0	7	0	0
T70	0	41	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank1_info0_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1232	0	0
T30	4892	2	0	0
T31	6278	2	0	0
T32	7655	0	0	0
T33	0	12	0	0
T38	0	6	0	0
T49	10569	13	0	0
T50	0	22	0	0
T51	0	2	0	0
T53	74737	269	0	0
T54	32063	0	0	0
T57	0	35	0	0
T70	0	49	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank1_info0_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1740	0	0
T30	4892	6	0	0
T31	6278	2	0	0
T32	7655	0	0	0
T33	0	30	0	0
T37	0	4	0	0
T49	10569	26	0	0
T50	0	5	0	0
T51	0	21	0	0
T53	74737	233	0	0
T54	32063	0	0	0
T69	0	1	0	0
T70	0	46	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank1_info0_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1295	0	0
T30	4892	6	0	0
T31	6278	2	0	0
T32	7655	0	0	0
T33	0	13	0	0
T37	0	6	0	0
T49	10569	44	0	0
T50	0	21	0	0
T51	0	19	0	0
T53	74737	237	0	0
T54	32063	0	0	0
T57	0	19	0	0
T70	0	42	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank1_info0_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1287	0	0
T30	4892	0	0	0
T31	6278	10	0	0
T32	7655	0	0	0
T33	0	18	0	0
T49	10569	38	0	0
T50	0	20	0	0
T51	0	46	0	0
T53	74737	282	0	0
T54	32063	0	0	0
T57	0	20	0	0
T69	0	8	0	0
T70	0	38	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0
T75	0	8	0	0

bank1_info0_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1707	0	0
T30	4892	5	0	0
T31	6278	4	0	0
T32	7655	0	0	0
T33	0	8	0	0
T49	10569	0	0	0
T50	0	14	0	0
T51	0	30	0	0
T53	74737	249	0	0
T54	32063	0	0	0
T57	0	32	0	0
T61	0	33	0	0
T69	0	5	0	0
T70	0	35	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank1_info0_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1202	0	0
T30	4892	3	0	0
T31	6278	4	0	0
T32	7655	0	0	0
T33	0	13	0	0
T49	10569	13	0	0
T50	0	35	0	0
T51	0	21	0	0
T53	74737	259	0	0
T54	32063	0	0	0
T57	0	19	0	0
T69	0	5	0	0
T70	0	30	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank1_info0_regwen_8_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	950	0	0
T30	4892	10	0	0
T31	6278	7	0	0
T32	7655	0	0	0
T33	0	25	0	0
T49	10569	0	0	0
T50	0	30	0	0
T51	0	38	0	0
T54	32063	0	0	0
T57	0	25	0	0
T61	0	23	0	0
T70	0	32	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0
T75	0	1	0	0
T76	1509	0	0	0
T77	807	0	0	0
T81	0	491	0	0

bank1_info0_regwen_9_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1340	0	0
T30	4892	7	0	0
T31	6278	13	0	0
T32	7655	0	0	0
T33	0	15	0	0
T37	0	5	0	0
T49	10569	29	0	0
T50	0	34	0	0
T51	0	29	0	0
T53	74737	292	0	0
T54	32063	0	0	0
T69	0	14	0	0
T70	0	57	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank1_info1_page_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2453	0	0
T30	4892	7	0	0
T31	6278	13	0	0
T32	7655	0	0	0
T33	0	3	0	0
T49	10569	16	0	0
T50	0	4	0	0
T51	0	14	0	0
T53	74737	281	0	0
T54	32063	0	0	0
T57	0	104	0	0
T69	0	26	0	0
T70	0	73	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank1_info1_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1002	0	0
T30	4892	7	0	0
T31	6278	6	0	0
T32	7655	0	0	0
T33	0	11	0	0
T37	0	10	0	0
T49	10569	32	0	0
T50	0	64	0	0
T51	0	8	0	0
T54	32063	0	0	0
T57	0	21	0	0
T69	0	1	0	0
T70	0	44	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0
T76	1509	0	0	0
T77	807	0	0	0

bank1_info2_page_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2466	0	0
T30	4892	10	0	0
T31	6278	29	0	0
T32	7655	0	0	0
T33	0	8	0	0
T37	0	6	0	0
T49	10569	28	0	0
T50	0	27	0	0
T51	0	54	0	0
T53	74737	243	0	0
T54	32063	0	0	0
T69	0	15	0	0
T70	0	212	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank1_info2_page_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1609	0	0
T30	4892	0	0	0
T31	6278	43	0	0
T32	7655	0	0	0
T33	0	50	0	0
T37	0	7	0	0
T38	0	7	0	0
T49	10569	42	0	0
T50	0	13	0	0
T51	0	42	0	0
T53	74737	268	0	0
T54	32063	0	0	0
T69	0	23	0	0
T70	0	122	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank1_info2_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	937	0	0
T30	4892	7	0	0
T31	6278	10	0	0
T32	7655	0	0	0
T33	0	27	0	0
T37	0	4	0	0
T49	10569	16	0	0
T50	0	52	0	0
T51	0	32	0	0
T54	32063	0	0	0
T57	0	16	0	0
T69	0	9	0	0
T70	0	50	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0
T76	1509	0	0	0
T77	807	0	0	0

bank1_info2_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1740	0	0
T30	4892	8	0	0
T31	6278	10	0	0
T32	7655	0	0	0
T33	0	42	0	0
T37	0	7	0	0
T49	10569	36	0	0
T50	0	23	0	0
T51	0	10	0	0
T53	74737	302	0	0
T54	32063	0	0	0
T69	0	6	0	0
T70	0	36	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

bank_cfg_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1742	0	0
T30	4892	2	0	0
T31	6278	11	0	0
T32	7655	0	0	0
T33	0	21	0	0
T37	0	7	0	0
T38	0	1	0	0
T49	10569	11	0	0
T50	0	28	0	0
T51	0	28	0	0
T53	74737	238	0	0
T54	32063	0	0	0
T70	0	37	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

default_region_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1870	0	0
T30	4892	3	0	0
T31	6278	19	0	0
T32	7655	0	0	0
T33	0	9	0	0
T37	0	4	0	0
T38	0	6	0	0
T49	10569	26	0	0
T50	0	17	0	0
T51	0	31	0	0
T53	74737	238	0	0
T54	32063	0	0	0
T69	0	12	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1972	0	0
T30	4892	4	0	0
T31	6278	6	0	0
T32	7655	0	0	0
T33	0	29	0	0
T38	0	2	0	0
T49	10569	24	0	0
T50	0	22	0	0
T51	0	3	0	0
T53	74737	406	0	0
T54	32063	0	0	0
T69	0	2	0	0
T70	0	50	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

fifo_lvl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1894	0	0
T30	4892	2	0	0
T31	6278	21	0	0
T32	7655	0	0	0
T33	0	6	0	0
T37	0	1	0	0
T49	10569	37	0	0
T50	0	25	0	0
T51	0	12	0	0
T53	74737	252	0	0
T54	32063	0	0	0
T57	0	28	0	0
T70	0	65	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

fifo_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1859	0	0
T30	4892	8	0	0
T31	6278	13	0	0
T32	7655	0	0	0
T33	0	31	0	0
T49	10569	8	0	0
T50	0	48	0	0
T51	0	38	0	0
T53	74737	312	0	0
T54	32063	0	0	0
T57	0	20	0	0
T69	0	7	0	0
T70	0	23	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

hw_info_cfg_override_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1843	0	0
T30	4892	2	0	0
T31	6278	16	0	0
T32	7655	0	0	0
T33	0	20	0	0
T38	0	7	0	0
T49	10569	27	0	0
T50	0	21	0	0
T51	0	46	0	0
T53	74737	260	0	0
T54	32063	0	0	0
T69	0	3	0	0
T70	0	59	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1548	0	0
T30	4892	6	0	0
T31	6278	36	0	0
T32	7655	0	0	0
T33	0	8	0	0
T37	0	15	0	0
T38	0	1	0	0
T49	10569	24	0	0
T50	0	8	0	0
T51	0	21	0	0
T54	32063	0	0	0
T69	0	32	0	0
T70	0	121	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0
T76	1509	0	0	0
T77	807	0	0	0

mp_region_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1952	0	0
T30	4892	6	0	0
T31	6278	23	0	0
T32	7655	0	0	0
T33	0	6	0	0
T37	0	2	0	0
T49	10569	29	0	0
T50	0	4	0	0
T51	0	15	0	0
T53	74737	253	0	0
T54	32063	0	0	0
T69	0	9	0	0
T70	0	94	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

mp_region_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1378	0	0
T30	4892	2	0	0
T31	6278	9	0	0
T32	7655	0	0	0
T33	0	14	0	0
T49	10569	36	0	0
T50	0	18	0	0
T51	0	6	0	0
T53	74737	245	0	0
T54	32063	0	0	0
T57	0	30	0	0
T69	0	18	0	0
T70	0	86	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

mp_region_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1776	0	0
T30	4892	4	0	0
T31	6278	12	0	0
T32	7655	0	0	0
T38	0	1	0	0
T49	10569	20	0	0
T50	0	17	0	0
T51	0	29	0	0
T53	74737	240	0	0
T54	32063	0	0	0
T57	0	22	0	0
T69	0	14	0	0
T70	0	82	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

mp_region_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1689	0	0
T30	4892	5	0	0
T31	6278	10	0	0
T32	7655	0	0	0
T33	0	48	0	0
T37	0	2	0	0
T38	0	1	0	0
T49	10569	10	0	0
T50	0	28	0	0
T51	0	27	0	0
T54	32063	0	0	0
T69	0	6	0	0
T70	0	62	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0
T76	1509	0	0	0
T77	807	0	0	0

mp_region_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1897	0	0
T30	4892	4	0	0
T31	6278	23	0	0
T32	7655	0	0	0
T33	0	38	0	0
T38	0	4	0	0
T49	10569	38	0	0
T50	0	9	0	0
T51	0	1	0	0
T53	74737	235	0	0
T54	32063	0	0	0
T69	0	3	0	0
T70	0	61	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

mp_region_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1485	0	0
T30	4892	1	0	0
T31	6278	23	0	0
T32	7655	0	0	0
T33	0	47	0	0
T37	0	2	0	0
T49	10569	38	0	0
T50	0	27	0	0
T51	0	18	0	0
T53	74737	337	0	0
T54	32063	0	0	0
T69	0	22	0	0
T70	0	62	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

mp_region_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1352	0	0
T30	4892	12	0	0
T31	6278	5	0	0
T32	7655	0	0	0
T33	0	17	0	0
T38	0	3	0	0
T49	10569	38	0	0
T50	0	23	0	0
T51	0	48	0	0
T53	74737	296	0	0
T54	32063	0	0	0
T57	0	18	0	0
T70	0	64	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

mp_region_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1428	0	0
T30	4892	10	0	0
T31	6278	16	0	0
T32	7655	0	0	0
T33	0	15	0	0
T37	0	8	0	0
T38	0	6	0	0
T49	10569	23	0	0
T50	0	13	0	0
T51	0	38	0	0
T53	74737	279	0	0
T54	32063	0	0	0
T69	0	13	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

mp_region_cfg_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2292	0	0
T30	4892	0	0	0
T31	6278	43	0	0
T32	7655	0	0	0
T33	0	37	0	0
T37	0	5	0	0
T49	10569	0	0	0
T50	0	40	0	0
T51	0	37	0	0
T53	74737	235	0	0
T54	32063	0	0	0
T57	0	116	0	0
T69	0	29	0	0
T70	0	167	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0
T75	0	2	0	0

mp_region_cfg_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2179	0	0
T30	4892	9	0	0
T31	6278	65	0	0
T32	7655	0	0	0
T33	0	45	0	0
T38	0	8	0	0
T49	10569	38	0	0
T50	0	1	0	0
T51	0	16	0	0
T53	74737	256	0	0
T54	32063	0	0	0
T69	0	26	0	0
T70	0	145	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

mp_region_cfg_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1792	0	0
T30	4892	10	0	0
T31	6278	11	0	0
T32	7655	0	0	0
T33	0	12	0	0
T37	0	13	0	0
T49	10569	6	0	0
T50	0	26	0	0
T51	0	17	0	0
T54	32063	0	0	0
T57	0	116	0	0
T69	0	1	0	0
T70	0	209	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0
T76	1509	0	0	0
T77	807	0	0	0

mp_region_cfg_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2710	0	0
T30	4892	0	0	0
T31	6278	11	0	0
T32	7655	0	0	0
T33	0	11	0	0
T37	0	1	0	0
T38	0	1	0	0
T49	10569	12	0	0
T50	0	18	0	0
T51	0	24	0	0
T53	74737	220	0	0
T54	32063	0	0	0
T69	0	23	0	0
T70	0	185	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

mp_region_cfg_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2792	0	0
T30	4892	8	0	0
T31	6278	33	0	0
T32	7655	0	0	0
T33	0	14	0	0
T37	0	6	0	0
T49	10569	46	0	0
T50	0	29	0	0
T51	0	38	0	0
T53	74737	291	0	0
T54	32063	0	0	0
T69	0	27	0	0
T70	0	244	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

mp_region_cfg_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2615	0	0
T30	4892	4	0	0
T31	6278	32	0	0
T32	7655	0	0	0
T33	0	11	0	0
T37	0	12	0	0
T49	10569	6	0	0
T50	0	49	0	0
T51	0	27	0	0
T53	74737	296	0	0
T54	32063	0	0	0
T57	0	46	0	0
T70	0	200	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

mp_region_cfg_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2361	0	0
T30	4892	7	0	0
T31	6278	31	0	0
T32	7655	0	0	0
T33	0	13	0	0
T37	0	8	0	0
T38	0	8	0	0
T49	10569	43	0	0
T50	0	12	0	0
T51	0	26	0	0
T54	32063	0	0	0
T69	0	7	0	0
T70	0	191	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0
T76	1509	0	0	0
T77	807	0	0	0

mp_region_cfg_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	2552	0	0
T30	4892	5	0	0
T31	6278	40	0	0
T32	7655	0	0	0
T33	0	17	0	0
T37	0	9	0	0
T38	0	3	0	0
T49	10569	55	0	0
T50	0	34	0	0
T51	0	9	0	0
T53	74737	236	0	0
T54	32063	0	0	0
T69	0	35	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

phy_alert_cfg_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1419	0	0
T30	4892	1	0	0
T31	6278	0	0	0
T32	7655	0	0	0
T33	0	18	0	0
T38	0	1	0	0
T49	10569	19	0	0
T50	0	39	0	0
T51	0	25	0	0
T53	74737	267	0	0
T54	32063	0	0	0
T61	0	3	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0
T81	0	982	0	0
T82	0	26	0	0

region_cfg_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1776	0	0
T30	4892	0	0	0
T31	6278	10	0	0
T32	7655	0	0	0
T33	0	34	0	0
T37	0	8	0	0
T38	0	1	0	0
T49	10569	30	0	0
T50	0	33	0	0
T51	0	6	0	0
T53	74737	253	0	0
T54	32063	0	0	0
T69	0	7	0	0
T70	0	52	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

region_cfg_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1678	0	0
T30	4892	4	0	0
T31	6278	14	0	0
T32	7655	0	0	0
T33	0	21	0	0
T37	0	7	0	0
T49	10569	29	0	0
T50	0	18	0	0
T51	0	13	0	0
T53	74737	234	0	0
T54	32063	0	0	0
T69	0	9	0	0
T70	0	38	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

region_cfg_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1164	0	0
T30	4892	8	0	0
T31	6278	2	0	0
T32	7655	0	0	0
T33	0	24	0	0
T37	0	4	0	0
T49	10569	0	0	0
T50	0	30	0	0
T51	0	28	0	0
T53	74737	276	0	0
T54	32063	0	0	0
T57	0	30	0	0
T69	0	8	0	0
T70	0	38	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

region_cfg_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1782	0	0
T30	4892	4	0	0
T31	6278	9	0	0
T32	7655	0	0	0
T33	0	12	0	0
T49	10569	22	0	0
T50	0	45	0	0
T51	0	11	0	0
T53	74737	281	0	0
T54	32063	0	0	0
T57	0	39	0	0
T70	0	53	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0
T75	0	1	0	0

region_cfg_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1748	0	0
T30	4892	6	0	0
T31	6278	7	0	0
T32	7655	0	0	0
T33	0	8	0	0
T38	0	2	0	0
T49	10569	25	0	0
T50	0	37	0	0
T51	0	60	0	0
T53	74737	261	0	0
T54	32063	0	0	0
T69	0	10	0	0
T70	0	42	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

region_cfg_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	467	0	0
T30	4892	3	0	0
T31	6278	9	0	0
T32	7655	0	0	0
T33	0	33	0	0
T37	0	5	0	0
T38	0	9	0	0
T49	10569	16	0	0
T50	0	31	0	0
T51	0	33	0	0
T54	32063	0	0	0
T57	0	19	0	0
T70	0	45	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0
T76	1509	0	0	0
T77	807	0	0	0

region_cfg_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1548	0	0
T30	4892	9	0	0
T31	6278	7	0	0
T32	7655	0	0	0
T33	0	18	0	0
T37	0	5	0	0
T38	0	8	0	0
T49	10569	27	0	0
T50	0	6	0	0
T51	0	7	0	0
T53	74737	246	0	0
T54	32063	0	0	0
T69	0	3	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

region_cfg_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1273	0	0
T30	4892	2	0	0
T31	6278	12	0	0
T32	7655	0	0	0
T33	0	26	0	0
T38	0	5	0	0
T49	10569	37	0	0
T50	0	10	0	0
T51	0	38	0	0
T53	74737	297	0	0
T54	32063	0	0	0
T69	0	8	0	0
T70	0	33	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0

scratch_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2308514	1675	0	0
T30	4892	10	0	0
T31	6278	4	0	0
T32	7655	0	0	0
T33	0	8	0	0
T38	0	4	0	0
T49	10569	0	0	0
T50	0	2	0	0
T51	0	8	0	0
T53	74737	271	0	0
T54	32063	0	0	0
T57	0	23	0	0
T69	0	7	0	0
T70	0	37	0	0
T71	892	0	0	0
T72	1253	0	0	0
T73	1286	0	0	0
T74	1107	0	0	0