Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total995010
Category 0995010

Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total995010
Severity 0995010

Summary for Assertions
NUMBERPERCENT
Total Number995100.00
Uncovered171.71
Success97898.29
Failure00.00
Incomplete151.51
Without Attempts00.00

Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered330.00
All Matches770.00
First Matches770.00
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ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETE
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.DataKnown_A 004102491811298835700
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.DepthKnown_A 0041024918140942344600
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.RvalidKnown_A 0041024918140942344600
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.WreadyKnown_A 0041024918140942344600
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.depthShallNotExceedParamDepth 004102491811298835700
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.DataKnown_A 004102491815095615200
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.DepthKnown_A 0041024918140942344600
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.RvalidKnown_A 0041024918140942344600
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.WreadyKnown_A 0041024918140942344600
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 004102491815095615200
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.CheckHotOne_A 0041052611340970037800
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.CheckNGreaterZero_A 001059105900
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.GntImpliesReady_A 00410526113285165900
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.GntImpliesValid_A 00410526113285165900
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.GrantKnown_A 0041052611340970037800
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.IdxKnown_A 0041052611340970037800
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.IndexIsCorrect_A 00410526113285165900
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.NoReadyValidNoGrant_A 0041052611330345000400
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReadyAndValidImplyGrant_A 00410526113285165900
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqAndReadyImplyGrant_A 00410526113285165900
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqImpliesValid_A 0041052611310165178700
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A 004105261132397601052
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ValidKnown_A 0041052611340970037800
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_state_regs.AssertConnected_A 001059105900
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_state_regs_A 0041052611340970037800
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.DataKnown_A 00410249181325843900
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.DepthKnown_A 0041024918140942344600
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.RvalidKnown_A 0041024918140942344600
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.WreadyKnown_A 0041024918140942344600
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 00410249181325843900
tb.dut.u_eflash.u_bank_sequence_fifo.DataKnown_A 004105261133500037800
tb.dut.u_eflash.u_bank_sequence_fifo.DepthKnown_A 0041052611340970037800
tb.dut.u_eflash.u_bank_sequence_fifo.RvalidKnown_A 0041052611340970037800
tb.dut.u_eflash.u_bank_sequence_fifo.WreadyKnown_A 0041052611340970037800
tb.dut.u_eflash.u_bank_sequence_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 004105261133500037800
tb.dut.u_eflash.u_disable_buf.NumCopiesMustBeGreaterZero_A 001059105900
tb.dut.u_eflash.u_disable_buf.OutputsKnown_A 0041052611340970037800
tb.dut.u_eflash.u_disable_buf.gen_no_flops.OutputDelay_A 0041052611340970037800
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A 001059105900
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A 004105261132278832000
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A 001059105900
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A 00410526113736816200
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A 001059105900
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A 00410526113808996800
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.DataKnown_A 0041052611311058479700
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.DepthKnown_A 0041052611340970037800
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.RvalidKnown_A 0041052611340970037800
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.WreadyKnown_A 0041052611340970037800
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 0041052611311058479700
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A 001059105900
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A 004105261137261825100
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A 001059105900
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A 00410526113571182800
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A 001059105900
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A 00410526113429879600
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A 001059105900
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A 00410526113435273800
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.DataKnown_A 004105261139061258300
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.DepthKnown_A 0041052611340970037800
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.RvalidKnown_A 0041052611340970037800
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.WreadyKnown_A 0041052611340970037800
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 004105261139061258300
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A 001059105900
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A 004105261136953282200
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.en2addrHit 004132421405474900
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.reAfterRv 004132421405474900
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.rePulse 004132421403788200
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_chk.PayLoadWidthCheck 001274127400
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.AllowedLatency_A 001274127400
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.MatchedWidthAssert 001274127400
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_err.dataWidthOnly32_A 001274127400
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A 001274127400
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck 001274127400
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.DataWidthCheck_A 001274127400
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.PayLoadWidthCheck 001274127400
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.wePulse 004132421401686700
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.NumCopiesMustBeGreaterZero_A 001059105900
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.OutputsKnown_A 0040487006540404433000
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.OutputDelay_A 0040487006540401218202766
tb.dut.u_eflash.u_scramble.gen_gf_mult.u_mult.IntegerLoops_A 001059105900
tb.dut.u_eflash.u_scramble.gen_gf_mult.u_mult.StagePow2_A 001059105900
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.CheckHotOne_A 0041052611340970037800
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.CheckNGreaterZero_A 001059105900
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.GntImpliesReady_A 004105261131675026200
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.GntImpliesValid_A 004105261131675026200
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.GrantKnown_A 0041052611340970037800
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.IdxKnown_A 0041052611340970037800
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.IndexIsCorrect_A 004105261131675026200
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.LockArbDecision_A 004105261131675026100
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.NoReadyValidNoGrant_A 0041052611337619984300
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.ReadyAndValidImplyGrant_A 004105261131675026200
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.ReqAndReadyImplyGrant_A 004105261131675026200
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.ReqImpliesValid_A 004105261133350053500
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.ReqStaysHighUntilGranted0_M 004105261131675026100
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.ValidKnown_A 0041052611340970037800
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.gen_data_port_assertion.DataFlow_A 004105261131675026200
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.CheckHotOne_A 0041052611340970037800
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.CheckNGreaterZero_A 001059105900
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.GntImpliesReady_A 004105261131675026200
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.GntImpliesValid_A 004105261131675026200
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.GrantKnown_A 0041052611340970037800
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.IdxKnown_A 0041052611340970037800
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.IndexIsCorrect_A 004105261131675026200
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.LockArbDecision_A 004105261131675026100
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.NoReadyValidNoGrant_A 0041052611337619984300
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReadyAndValidImplyGrant_A 004105261131675026200
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReqAndReadyImplyGrant_A 004105261131675026200
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReqImpliesValid_A 004105261133350053500
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReqStaysHighUntilGranted0_M 004105261131675026100
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.ValidKnown_A 0041052611340970037800
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.gen_data_port_assertion.DataFlow_A 004105261131675026200
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.CheckHotOne_A 0041052611340970037800
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.CheckNGreaterZero_A 001059105900
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.GntImpliesReady_A 004105261131595814600
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.GntImpliesValid_A 004105261131595814600
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.GrantKnown_A 0041052611340970037800
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.IdxKnown_A 0041052611340970037800
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.IndexIsCorrect_A 004105261131595814600
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.LockArbDecision_A 004105261131595814600
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.NoReadyValidNoGrant_A 0041052611337778407600
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.ReadyAndValidImplyGrant_A 004105261131595814600
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.ReqAndReadyImplyGrant_A 004105261131595814600
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.ReqImpliesValid_A 004105261133191630200
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.ReqStaysHighUntilGranted0_M 004105261131595814600
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.ValidKnown_A 0041052611340970037800
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.gen_data_port_assertion.DataFlow_A 004105261131595814600
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.CheckHotOne_A 0041052611340970037800
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.CheckNGreaterZero_A 001059105900
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.GntImpliesReady_A 004105261131595814600
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.GntImpliesValid_A 004105261131595814600
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.GrantKnown_A 0041052611340970037800
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.IdxKnown_A 0041052611340970037800
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.IndexIsCorrect_A 004105261131595814600
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.LockArbDecision_A 004105261131595814600
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.NoReadyValidNoGrant_A 0041052611337778407600
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReadyAndValidImplyGrant_A 004105261131595814600
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReqAndReadyImplyGrant_A 004105261131595814600
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReqImpliesValid_A 004105261133191630200
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReqStaysHighUntilGranted0_M 004105261131595814600
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.ValidKnown_A 0041052611340970037800
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.gen_data_port_assertion.DataFlow_A 004105261131595814600
tb.dut.u_flash_hw_if.DisableChk_A 003983938965675706046
tb.dut.u_flash_hw_if.ProgRdVerify_A 00394345569204353600
tb.dut.u_flash_hw_if.u_addr_sync_reqack.SyncReqAckAckNeedsReq 00410526390898000
tb.dut.u_flash_hw_if.u_addr_sync_reqack.SyncReqAckHoldReq 00410430806864900
tb.dut.u_flash_hw_if.u_data_sync_reqack.SyncReqAckAckNeedsReq 00410526390894400
tb.dut.u_flash_hw_if.u_data_sync_reqack.SyncReqAckHoldReq 00402511906864800
tb.dut.u_flash_hw_if.u_rma_state_regs.AssertConnected_A 001059105900
tb.dut.u_flash_hw_if.u_rma_state_regs_A 0041052639040970065500
tb.dut.u_flash_hw_if.u_state_regs.AssertConnected_A 001059105900
tb.dut.u_flash_hw_if.u_state_regs_A 0041052639040970065500
tb.dut.u_flash_hw_if.u_sync_rma_req.NumCopiesMustBeGreaterZero_A 001059105900
tb.dut.u_flash_hw_if.u_sync_rma_req.OutputsKnown_A 0040487034240404460700
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.OutputDelay_A 0040487034240401244402766
tb.dut.u_flash_mp.BankEraseData_A 00410526390845545300
tb.dut.u_flash_mp.BankEraseInfo_A 004105263901160058000
tb.dut.u_flash_mp.DataReqToInfo_A 0041052639027365287600
tb.dut.u_flash_mp.InReqOutReq_A 0041052639030843745200
tb.dut.u_flash_mp.InfoReqToData_A 004105263903478457600
tb.dut.u_flash_mp.NoReqWhenErr_A 0040502767811167000
tb.dut.u_flash_mp.bkEraseEnOnehot_A 004105263902005603300
tb.dut.u_flash_mp.hwInfoRuleOnehot_A 0041052639015628120200
tb.dut.u_flash_mp.invalidReqOnehot_A 0041052639030832574300
tb.dut.u_flash_mp.requestTypesOnehot_A 0041052639030832574300
tb.dut.u_intr_corr_err.IntrTKind_A 001059105900
tb.dut.u_intr_op_done.IntrTKind_A 001059105900
tb.dut.u_intr_prog_empty.IntrTKind_A 001059105900
tb.dut.u_intr_prog_lvl.IntrTKind_A 001059105900
tb.dut.u_intr_rd_full.IntrTKind_A 001059105900
tb.dut.u_intr_rd_lvl.IntrTKind_A 001059105900
tb.dut.u_lc_escalation_en_sync.NumCopiesMustBeGreaterZero_A 001059105900
tb.dut.u_lc_escalation_en_sync.OutputsKnown_A 0040484538340401964800
tb.dut.u_lc_escalation_en_sync.gen_flops.OutputDelay_A 0040484538340398763502616
tb.dut.u_lc_seed_hw_rd_en_sync.NumCopiesMustBeGreaterZero_A 001059105900
tb.dut.u_lc_seed_hw_rd_en_sync.OutputsKnown_A 0040487034240404460700
tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.OutputDelay_A 0040487034240401244402766
tb.dut.u_prog_fifo.DataKnown_A 0041052611319551800000
tb.dut.u_prog_fifo.DepthKnown_A 0041052611340970037800
tb.dut.u_prog_fifo.RvalidKnown_A 0041052611340970037800
tb.dut.u_prog_fifo.WreadyKnown_A 0041052611340970037800
tb.dut.u_prog_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 0041052611319551800000
tb.dut.u_prog_tl_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A 001059105900
tb.dut.u_prog_tl_gate.u_err_en_sync.OutputsKnown_A 0040487006540404433000
tb.dut.u_prog_tl_gate.u_err_en_sync.gen_no_flops.OutputDelay_A 0040487006540404433000
tb.dut.u_prog_tl_gate.u_state_regs.AssertConnected_A 001059105900
tb.dut.u_prog_tl_gate.u_state_regs_A 0041052611340970037800
tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A 001059105900
tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck 001059105900
tb.dut.u_reg_core.en2addrHit 004132424172575265100
tb.dut.u_reg_core.reAfterRv 004132424172575262900
tb.dut.u_reg_core.rePulse 004132424172338963700
tb.dut.u_reg_core.u_chk.PayLoadWidthCheck 001274127400
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.CheckSwAccessIsLegal_A 001274127400
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.MubiIsNotYetSupported_A 0041324241741233050200
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.CheckSwAccessIsLegal_A 001274127400
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.MubiIsNotYetSupported_A 0041324241741233050200
tb.dut.u_reg_core.u_reg_if.AllowedLatency_A 001274127400
tb.dut.u_reg_core.u_reg_if.MatchedWidthAssert 001274127400
tb.dut.u_reg_core.u_reg_if.u_err.dataWidthOnly32_A 001274127400
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A 001274127400
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck 001274127400
tb.dut.u_reg_core.u_rsp_intg_gen.DataWidthCheck_A 001274127400
tb.dut.u_reg_core.u_rsp_intg_gen.PayLoadWidthCheck 001274127400
tb.dut.u_reg_core.u_socket.NotOverflowed_A 0041324214041233022500
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DataKnown_A 004132421403287651100
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DepthKnown_A 0041324214041233022500
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.RvalidKnown_A 0041324214041233022500
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.WreadyKnown_A 0041324214041233022500
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass 001274127400
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DataKnown_A 004132421403733384100
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DepthKnown_A 0041324214041233022500
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.RvalidKnown_A 0041324214041233022500
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.WreadyKnown_A 0041324214041233022500
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass 001274127400
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A 00413242140241893700
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A 0041324214041233022500
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A 0041324214041233022500
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A 0041324214041233022500
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 001274127400
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A 00413242140265139800
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A 0041324214041233022500
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A 0041324214041233022500
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A 0041324214041233022500
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 001274127400
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A 00413242140419250900
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A 0041324214041233022500
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A 0041324214041233022500
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A 0041324214041233022500
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 001274127400
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A 00413242140391946200
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A 0041324214041233022500
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A 0041324214041233022500
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A 0041324214041233022500
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 001274127400
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.DataKnown_A 004132421402619609200
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.DepthKnown_A 0041324214041233022500
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.RvalidKnown_A 0041324214041233022500
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.WreadyKnown_A 0041324214041233022500
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 001274127400
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.DataKnown_A 004132421403076298100
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.DepthKnown_A 0041324214041233022500
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.RvalidKnown_A 0041324214041233022500
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.WreadyKnown_A 0041324214041233022500
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 001274127400
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.DataWidthCheck_A 001274127400
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.PayLoadWidthCheck 001274127400
tb.dut.u_reg_core.u_socket.maxN 001274127400
tb.dut.u_reg_core.wePulse 00413242417236299200
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.InfoNoBiggerThanData_A 001059105900
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi.OutputsKnown_A 0041052639040970065500
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi.OutputsKnown_A 0041052639040970065500
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.InfoNoBiggerThanData_A 001059105900
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi.OutputsKnown_A 0041052639040970065500
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi.OutputsKnown_A 0041052639040970065500
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.InfoNoBiggerThanData_A 001059105900
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi.OutputsKnown_A 0041052639040970065500
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi.OutputsKnown_A 0041052639040970065500
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.InfoNoBiggerThanData_A 001059105900
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi.OutputsKnown_A 0041052639040970065500
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi.OutputsKnown_A 0041052639040970065500
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.InfoNoBiggerThanData_A 001059105900
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi.OutputsKnown_A 0041052639040970065500
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi.OutputsKnown_A 0041052639040970065500
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.InfoNoBiggerThanData_A 001059105900
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi.OutputsKnown_A 0041052639040970065500
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi.OutputsKnown_A 0041052639040970065500
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.NumCopiesMustBeGreaterZero_A 001059105900
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.OutputsKnown_A 0040487034240404460700
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.OutputDelay_A 0040487034240401244402766
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.NumCopiesMustBeGreaterZero_A 001059105900
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.OutputsKnown_A 0040487034240404460700
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.OutputDelay_A 0040487034240401244402766
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.NumCopiesMustBeGreaterZero_A 001059105900
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.OutputsKnown_A 0040487034240404460700
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.OutputDelay_A 0040487034240401244402766
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.NumCopiesMustBeGreaterZero_A 001059105900
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.OutputsKnown_A 0040487034240404460700
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.OutputDelay_A 0040487034240401244402766
tb.dut.u_sw_rd_fifo.DataKnown_A 004105261135056786800
tb.dut.u_sw_rd_fifo.DepthKnown_A 0041052611340970037800
tb.dut.u_sw_rd_fifo.RvalidKnown_A 0041052611340970037800
tb.dut.u_sw_rd_fifo.WreadyKnown_A 0041052611340970037800
tb.dut.u_sw_rd_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 004105261135056786800
tb.dut.u_tl_adapter_eflash.AddrOutKnown_A 0041052611340970037800
tb.dut.u_tl_adapter_eflash.DataIntgOptions_A 001059105900
tb.dut.u_tl_adapter_eflash.ReqOutKnown_A 0041052611340970037800
tb.dut.u_tl_adapter_eflash.SramDwHasByteGranularity_A 001059105900
tb.dut.u_tl_adapter_eflash.SramDwIsMultipleOfTlulWidth_A 001059105900
tb.dut.u_tl_adapter_eflash.TlOutKnown_A 0041052611340970037800
tb.dut.u_tl_adapter_eflash.TlOutPayloadKnown_A 00410526113630184600
tb.dut.u_tl_adapter_eflash.TlOutPayloadKnown_AKnownEnable 0041052611340970037800
tb.dut.u_tl_adapter_eflash.WdataOutKnown_A 0041052611340970037800
tb.dut.u_tl_adapter_eflash.WeOutKnown_A 0041052611340970037800
tb.dut.u_tl_adapter_eflash.WmaskOutKnown_A 0041052611340970037800
tb.dut.u_tl_adapter_eflash.adapterNoReadOrWrite 001059105900
tb.dut.u_tl_adapter_eflash.gen_cmd_intg_check.u_cmd_intg_chk.PayLoadWidthCheck 001059105900
tb.dut.u_tl_adapter_eflash.rvalidHighReqFifoEmpty 00410526113459401800
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