| | | | | | |
tb.dut.tlul_assert_device.gen_assert_final[230].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[231].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[232].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[233].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[234].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[235].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[236].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[237].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[238].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[239].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[23].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[240].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[241].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[242].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[243].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[244].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[245].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[246].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[247].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[248].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[249].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[24].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[250].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[251].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[252].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[253].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[254].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[255].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[25].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[26].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[27].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[28].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[29].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[2].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[30].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[31].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[32].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[33].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[34].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[35].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[36].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[37].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[38].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[39].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[3].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[41].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[42].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
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tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 1269 | 1269 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.aDataKnown_M
| 0 | 0 | 413242851 | 4892533 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A
| 0 | 0 | 413242140 | 5831 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.contigMask_M
| 0 | 0 | 413242851 | 30181463 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.dDataKnown_A
| 0 | 0 | 412965919 | 31109575 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A
| 0 | 0 | 413242140 | 4435 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.legalAParam_M
| 0 | 0 | 413242851 | 32876517 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.legalDParam_A
| 0 | 0 | 413242851 | 37333857 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M
| 0 | 0 | 413242851 | 32876517 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A
| 0 | 0 | 413242851 | 37333857 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.respOpcode_A
| 0 | 0 | 413242851 | 37333857 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A
| 0 | 0 | 413242851 | 37333857 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A
| 0 | 0 | 413242140 | 4642 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A
| 0 | 0 | 413242140 | 5376 | 0 | 0 |
|
tb.dut.tlul_assert_device.p_dbw.TlDbw_A
| 0 | 0 | 1274 | 1274 | 0 | 0 |
|
tb.dut.u_ctrl_arb.u_state_regs.AssertConnected_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_ctrl_arb.u_state_regs_A
| 0 | 0 | 410526390 | 409700655 | 0 | 0 |
|
tb.dut.u_disable_buf.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_disable_buf.OutputsKnown_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_disable_buf.gen_no_flops.OutputDelay_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.ArbCntMax_A
| 0 | 0 | 410526113 | 2269810 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.CtrlPrio_A
| 0 | 0 | 410526113 | 2269809 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.HostTransIdleChk_A
| 0 | 0 | 410526113 | 23317924 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.NoRemainder_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.OneHotReqs_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.Pow2Multiple_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.RdTxnCheck_A
| 0 | 0 | 410249181 | 409423446 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.OneDonePerTxn_A
| 0 | 0 | 410526113 | 1218268 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.PostPackRule_A
| 0 | 0 | 410526113 | 17724 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.PrePackRule_A
| 0 | 0 | 410526113 | 8756 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.WidthCheck_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_state_regs.AssertConnected_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_state_regs_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.OutputsKnown_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_no_flops.OutputDelay_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckHotOne_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesReady_A
| 0 | 0 | 410526113 | 125421855 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesValid_A
| 0 | 0 | 410526113 | 125421855 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GrantKnown_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IdxKnown_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IndexIsCorrect_A
| 0 | 0 | 410526113 | 125421855 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A
| 0 | 0 | 410526113 | 47155485 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.Priority_A
| 0 | 0 | 410526113 | 131673159 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A
| 0 | 0 | 410526113 | 125421855 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A
| 0 | 0 | 410526113 | 125421855 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqImpliesValid_A
| 0 | 0 | 410526113 | 131673159 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ValidKnown_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckHotOne_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesReady_A
| 0 | 0 | 410526113 | 125225850 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesValid_A
| 0 | 0 | 410526113 | 125225850 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GrantKnown_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IdxKnown_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IndexIsCorrect_A
| 0 | 0 | 410526113 | 125225850 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A
| 0 | 0 | 410526113 | 47155533 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.Priority_A
| 0 | 0 | 410526113 | 131477106 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A
| 0 | 0 | 410526113 | 125225850 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A
| 0 | 0 | 410526113 | 125225850 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqImpliesValid_A
| 0 | 0 | 410526113 | 131477106 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ValidKnown_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.BufferMatchEcc_A
| 0 | 0 | 410526113 | 831447 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.ExclusiveOps_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.ExclusiveProgHazard_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.ExclusiveState_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.ForwardCheck_A
| 0 | 0 | 410526113 | 2482132 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.IdleCheck_A
| 0 | 0 | 410526113 | 54252351 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.MaxBufs_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.OneHotAlloc_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.OneHotMatch_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.OneHotRspMatch_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.OneHotUpdate_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf.AllocCheck_A
| 0 | 0 | 410526113 | 723370 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf.UpdateCheck_A
| 0 | 0 | 410526113 | 723370 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf.AllocCheck_A
| 0 | 0 | 410526113 | 723299 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf.UpdateCheck_A
| 0 | 0 | 410526113 | 723297 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf.AllocCheck_A
| 0 | 0 | 410526113 | 723231 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf.UpdateCheck_A
| 0 | 0 | 410526113 | 723225 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf.AllocCheck_A
| 0 | 0 | 410526113 | 722555 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf.UpdateCheck_A
| 0 | 0 | 410526113 | 722551 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.DataKnown_A
| 0 | 0 | 410526113 | 13252093 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.DepthKnown_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.RvalidKnown_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.WreadyKnown_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.gen_normal_fifo.depthShallNotExceedParamDepth
| 0 | 0 | 410526113 | 13252093 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.BufferDecrUnderRun_A
| 0 | 0 | 410526113 | 3723890 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.BufferDepRsp_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.BufferIncrOverFlow_A
| 0 | 0 | 410526113 | 3723903 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.DepBufferRspOrder_A
| 0 | 0 | 410526114 | 9206190 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.DataKnown_A
| 0 | 0 | 410249181 | 14390732 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.DepthKnown_A
| 0 | 0 | 410249181 | 409423446 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.RvalidKnown_A
| 0 | 0 | 410249181 | 409423446 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.WreadyKnown_A
| 0 | 0 | 410249181 | 409423446 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.depthShallNotExceedParamDepth
| 0 | 0 | 410249181 | 14390732 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.DataKnown_A
| 0 | 0 | 410249181 | 54244206 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.DepthKnown_A
| 0 | 0 | 410249181 | 409423446 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.RvalidKnown_A
| 0 | 0 | 410249181 | 409423446 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.WreadyKnown_A
| 0 | 0 | 410249181 | 409423446 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.depthShallNotExceedParamDepth
| 0 | 0 | 410249181 | 54244206 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.CheckHotOne_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.CheckNGreaterZero_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.GntImpliesReady_A
| 0 | 0 | 410526113 | 2860386 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.GntImpliesValid_A
| 0 | 0 | 410526113 | 2860386 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.GrantKnown_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.IdxKnown_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.IndexIsCorrect_A
| 0 | 0 | 410526113 | 2860386 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.NoReadyValidNoGrant_A
| 0 | 0 | 410526113 | 304145742 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReadyAndValidImplyGrant_A
| 0 | 0 | 410526113 | 2860386 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqAndReadyImplyGrant_A
| 0 | 0 | 410526113 | 2860386 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqImpliesValid_A
| 0 | 0 | 410526113 | 99986623 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.RoundRobin_A
| 0 | 0 | 410526113 | 36830 | 0 | 1052 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ValidKnown_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_state_regs.AssertConnected_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_state_regs_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.DataKnown_A
| 0 | 0 | 410249181 | 2919608 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.DepthKnown_A
| 0 | 0 | 410249181 | 409423446 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.RvalidKnown_A
| 0 | 0 | 410249181 | 409423446 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.WreadyKnown_A
| 0 | 0 | 410249181 | 409423446 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.depthShallNotExceedParamDepth
| 0 | 0 | 410249181 | 2919608 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.ArbCntMax_A
| 0 | 0 | 410526113 | 2193677 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.CtrlPrio_A
| 0 | 0 | 410526113 | 2193677 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.HostTransIdleChk_A
| 0 | 0 | 410526113 | 23240051 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.NoRemainder_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.OneHotReqs_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.Pow2Multiple_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.RdTxnCheck_A
| 0 | 0 | 410249181 | 409423446 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.OneDonePerTxn_A
| 0 | 0 | 410526113 | 1184201 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.PostPackRule_A
| 0 | 0 | 410526113 | 12521 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.PrePackRule_A
| 0 | 0 | 410526113 | 5931 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.WidthCheck_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_state_regs.AssertConnected_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_state_regs_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.NumCopiesMustBeGreaterZero_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.OutputsKnown_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_no_flops.OutputDelay_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckHotOne_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesReady_A
| 0 | 0 | 410526113 | 104978175 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesValid_A
| 0 | 0 | 410526113 | 104978175 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GrantKnown_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IdxKnown_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IndexIsCorrect_A
| 0 | 0 | 410526113 | 104978175 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A
| 0 | 0 | 410526113 | 43980181 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.Priority_A
| 0 | 0 | 410526113 | 111084607 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A
| 0 | 0 | 410526113 | 104978175 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A
| 0 | 0 | 410526113 | 104978175 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqImpliesValid_A
| 0 | 0 | 410526113 | 111084607 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ValidKnown_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckHotOne_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesReady_A
| 0 | 0 | 410526113 | 104978175 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesValid_A
| 0 | 0 | 410526113 | 104978175 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GrantKnown_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IdxKnown_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IndexIsCorrect_A
| 0 | 0 | 410526113 | 104978175 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A
| 0 | 0 | 410526113 | 43980181 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.Priority_A
| 0 | 0 | 410526113 | 111084607 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A
| 0 | 0 | 410526113 | 104978175 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A
| 0 | 0 | 410526113 | 104978175 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqImpliesValid_A
| 0 | 0 | 410526113 | 111084607 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ValidKnown_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.BufferMatchEcc_A
| 0 | 0 | 410526113 | 782206 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ExclusiveOps_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ExclusiveProgHazard_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ExclusiveState_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ForwardCheck_A
| 0 | 0 | 410526113 | 1994038 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.IdleCheck_A
| 0 | 0 | 410526113 | 50965187 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.MaxBufs_A
| 0 | 0 | 1059 | 1059 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotAlloc_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotMatch_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotRspMatch_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotUpdate_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf.AllocCheck_A
| 0 | 0 | 410526113 | 713044 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf.UpdateCheck_A
| 0 | 0 | 410526113 | 713044 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf.AllocCheck_A
| 0 | 0 | 410526113 | 713121 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf.UpdateCheck_A
| 0 | 0 | 410526113 | 713120 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf.AllocCheck_A
| 0 | 0 | 410526113 | 712994 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf.UpdateCheck_A
| 0 | 0 | 410526113 | 712993 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf.AllocCheck_A
| 0 | 0 | 410526113 | 712589 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf.UpdateCheck_A
| 0 | 0 | 410526113 | 712587 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.DataKnown_A
| 0 | 0 | 410526113 | 11647671 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.DepthKnown_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.RvalidKnown_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.WreadyKnown_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.gen_normal_fifo.depthShallNotExceedParamDepth
| 0 | 0 | 410526113 | 11647671 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep.BufferDecrUnderRun_A
| 0 | 0 | 410526113 | 3633950 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep.BufferDepRsp_A
| 0 | 0 | 410526113 | 409700378 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep.BufferIncrOverFlow_A
| 0 | 0 | 410526113 | 3633955 | 0 | 0 |
|
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep.DepBufferRspOrder_A
| 0 | 0 | 410526113 | 8196158 | 0 | 0 |
|