FLASH_CTRL Simulation Results

Monday April 15 2024 18:56:04 UTC

GitHub Revision: 9f4903e77a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 40268988864630991006175718979742731758115610160637428218057845043020955930762

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	4.635m	3.414ms	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.400s	185.008us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	44.880s	27.011us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.500s	56.712us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.406m	3.282ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.084m	3.271ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.800s	205.108us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.500s	56.712us	20	20	100.00
		flash_ctrl_csr_aliasing	1.084m	3.271ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.480s	15.149us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.770s	28.503us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.780s	21.834us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.028m	255.686us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	42.558m	676.851ms	3	3	100.00
		flash_ctrl_hw_rma_reset	16.757m	480.330ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.790s	59.706us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	41.199m	253.984ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.029m	11.216ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	15.900s	202.462us	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.196h	195.649ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	3.392m	5.632ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	37.980s	117.438us	40	40	100.00
		flash_ctrl_rw_evict_all_en	35.110s	456.932us	40	40	100.00
		flash_ctrl_re_evict	40.470s	156.371us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.935m	2.091ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.935m	2.091ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	15.873m	29.610ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	32.290s	2.377ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	24.026m	241.854us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	41.518m	29.597ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	16.789m	398.847us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	47.362m	2.119ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.700s	19.599us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.689m	1.543ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.460s	59.685us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.500s	28.755us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	28.675m	1.428ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.065m	11.644ms	50	50	100.00
		flash_ctrl_otp_reset	2.256m	43.895us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	42.558m	676.851ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	3.403m	1.159ms	40	40	100.00
		flash_ctrl_intr_wr	2.572m	68.817ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	5.881m	34.049ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	9.588m	216.692ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.594m	4.080ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.314m	7.937ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.650s	19.075us	5	5	100.00
		flash_ctrl_ro_derr	2.984m	611.899us	10	10	100.00
		flash_ctrl_rw_derr	11.446m	7.455ms	10	10	100.00
		flash_ctrl_derr_detect	1.803m	209.348us	5	5	100.00
		flash_ctrl_integrity	12.473m	16.866ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.800s	44.566us	5	5	100.00
		flash_ctrl_ro_serr	2.787m	3.601ms	10	10	100.00
		flash_ctrl_rw_serr	11.252m	27.712ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.366m	1.738ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.251m	3.133ms	5	5	100.00
V2	scramble	flash_ctrl_wo	4.088m	5.824ms	20	20	100.00
		flash_ctrl_write_word_sweep	16.970s	133.880us	1	1	100.00
		flash_ctrl_read_word_sweep	13.340s	16.520us	1	1	100.00
		flash_ctrl_ro	2.482m	2.322ms	20	20	100.00
		flash_ctrl_rw	11.113m	17.603ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	38.760s	791.314us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	17.349m	157.493ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	4.966m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.820s	200.586us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.840s	55.117us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	19.070s	276.435us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	19.070s	276.435us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	44.880s	27.011us	5	5	100.00
		flash_ctrl_csr_rw	17.500s	56.712us	20	20	100.00
		flash_ctrl_csr_aliasing	1.084m	3.271ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.550s	833.615us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	44.880s	27.011us	5	5	100.00
		flash_ctrl_csr_rw	17.500s	56.712us	20	20	100.00
		flash_ctrl_csr_aliasing	1.084m	3.271ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.550s	833.615us	20	20	100.00
V2		TOTAL			1013	1013	100.00
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	15.830s	11.072us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	15.830s	11.072us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	15.830s	11.072us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	15.830s	11.072us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.030s	43.212us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.339h	1.079ms	5	5	100.00
		flash_ctrl_tl_intg_err	14.987m	681.714us	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	14.987m	681.714us	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	14.987m	681.714us	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	31.720s	111.043us	3	3	100.00
		flash_ctrl_wr_intg	15.060s	82.814us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	4.635m	3.414ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.256m	43.895us	80	80	100.00
		flash_ctrl_disable	22.460s	59.685us	50	50	100.00
		flash_ctrl_sec_info_access	1.494m	6.251ms	50	50	100.00
		flash_ctrl_connect	16.500s	28.755us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	13.890s	19.436us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.500s	56.712us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.830s	11.072us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.500s	56.712us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.830s	11.072us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.500s	56.712us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	15.830s	11.072us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.460s	59.685us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	31.720s	111.043us	3	3	100.00
		flash_ctrl_access_after_disable	13.700s	102.915us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.460s	59.685us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	32.290s	2.377ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.113m	17.603ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	11.252m	27.712ms	10	10	100.00
		flash_ctrl_rw_derr	11.446m	7.455ms	10	10	100.00
		flash_ctrl_integrity	12.473m	16.866ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	42.558m	676.851ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.339h	1.079ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.339h	1.079ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.339h	1.079ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.339h	1.079ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	42.540s	857.043us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.110s	15.021us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.730s	44.049us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.339h	1.079ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.339h	1.079ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.339h	1.079ms	5	5	100.00
V2S		TOTAL			144	144	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	42.370s	47.579us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1278	1278	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	55	100.00
V2S	12	12	12	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.54	95.83	94.19	98.85	92.52	98.29	98.01	98.12

Past Results

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• 2024.04.12_19.13.20
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