FLASH_CTRL Simulation Results

Tuesday April 16 2024 19:02:32 UTC

GitHub Revision: `1c75f24e99`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 47053888840936652465110085351243654616760492049444303115123736462709488656445

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.728m	221.221us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.260s	224.827us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	45.780s	390.055us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.950s	73.434us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.056m	2.525ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.096m	1.286ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.330s	94.855us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.950s	73.434us	20	20	100.00
		flash_ctrl_csr_aliasing	1.096m	1.286ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.530s	46.167us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.760s	49.700us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.770s	45.262us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.056m	135.362us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	32.875m	275.601ms	3	3	100.00
		flash_ctrl_hw_rma_reset	15.743m	90.159ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.530s	15.766us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	47.794m	287.293ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	9.835m	9.770ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	1.762m	1.234ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	56.407m	49.894ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.444m	722.354us	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	37.850s	397.480us	40	40	100.00
		flash_ctrl_rw_evict_all_en	37.920s	1.359ms	38	40	95.00
		flash_ctrl_re_evict	39.080s	268.743us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	10.419m	5.534ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	10.419m	5.534ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	19.203m	42.588ms	18	20	90.00
V2	fetch_code	flash_ctrl_fetch_code	30.400s	1.633ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	20.406m	1.032ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	38.595m	26.781ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	17.723m	459.752us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	50.130m	661.079us	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.770s	15.344us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.577m	2.180ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.730s	49.742us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.490s	27.399us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	24.247m	1.818ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.562m	31.579ms	50	50	100.00
		flash_ctrl_otp_reset	2.260m	139.290us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	32.875m	275.601ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	3.741m	1.190ms	40	40	100.00
		flash_ctrl_intr_wr	1.858m	48.102ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	5.979m	40.848ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	7.612m	152.475ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.605m	1.136ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.205m	828.141us	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.740s	33.851us	5	5	100.00
		flash_ctrl_ro_derr	2.371m	662.911us	10	10	100.00
		flash_ctrl_rw_derr	11.350m	14.759ms	10	10	100.00
		flash_ctrl_derr_detect	1.746m	306.998us	5	5	100.00
		flash_ctrl_integrity	11.678m	17.856ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.900s	52.547us	5	5	100.00
		flash_ctrl_ro_serr	2.653m	616.493us	10	10	100.00
		flash_ctrl_rw_serr	11.017m	6.428ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.352m	3.601ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.595m	3.580ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.510m	13.228ms	20	20	100.00
		flash_ctrl_write_word_sweep	16.910s	119.986us	1	1	100.00
		flash_ctrl_read_word_sweep	13.160s	14.921us	1	1	100.00
		flash_ctrl_ro	2.081m	764.747us	20	20	100.00
		flash_ctrl_rw	10.112m	13.524ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	40.510s	642.741us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	17.380m	82.137ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.024m	10.013ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.580s	269.236us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.960s	150.082us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	19.380s	225.003us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	19.380s	225.003us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	45.780s	390.055us	5	5	100.00
		flash_ctrl_csr_rw	17.950s	73.434us	20	20	100.00
		flash_ctrl_csr_aliasing	1.096m	1.286ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.790s	868.754us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	45.780s	390.055us	5	5	100.00
		flash_ctrl_csr_rw	17.950s	73.434us	20	20	100.00
		flash_ctrl_csr_aliasing	1.096m	1.286ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.790s	868.754us	20	20	100.00
V2		TOTAL			1009	1013	99.61
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.020s	21.060us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.020s	21.060us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.020s	21.060us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.020s	21.060us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	15.880s	28.254us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.336h	2.330ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.101m	2.796ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.101m	2.796ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.101m	2.796ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	31.500s	697.919us	3	3	100.00
		flash_ctrl_wr_intg	14.690s	188.647us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.728m	221.221us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.260m	139.290us	80	80	100.00
		flash_ctrl_disable	22.730s	49.742us	50	50	100.00
		flash_ctrl_sec_info_access	1.421m	42.608ms	50	50	100.00
		flash_ctrl_connect	16.490s	27.399us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	13.950s	70.666us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.950s	73.434us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.020s	21.060us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.950s	73.434us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.020s	21.060us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.950s	73.434us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.020s	21.060us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.730s	49.742us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	31.500s	697.919us	3	3	100.00
		flash_ctrl_access_after_disable	13.540s	50.385us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.730s	49.742us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	30.400s	1.633ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	10.112m	13.524ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	11.017m	6.428ms	10	10	100.00
		flash_ctrl_rw_derr	11.350m	14.759ms	10	10	100.00
		flash_ctrl_integrity	11.678m	17.856ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	32.875m	275.601ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.336h	2.330ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.336h	2.330ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.336h	2.330ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.336h	2.330ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	1.350m	875.039us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	15.300s	24.885us	4	5	80.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.520s	36.959us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.336h	2.330ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.336h	2.330ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.336h	2.330ms	5	5	100.00
V2S		TOTAL			143	144	99.31
V3	asymmetric_read_path	flash_ctrl_rd_ooo	45.420s	79.275us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1273	1278	99.61

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	53	96.36
V2S	12	12	11	91.67
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.37	95.78	93.95	98.85	91.84	98.07	98.01	98.06

Failure Buckets

UVM_FATAL (flash_ctrl_mp_regions_vseq.sv:196) [flash_ctrl_mp_regions_vseq] wait timeout for alert_count == exp_alertcnt after do_mp_reg() alert_cnt:* exp_alert_cnt:* has 2 failures:

Test flash_ctrl_mp_regions has 2 failures.

10.flash_ctrl_mp_regions.90473262264215313649931703661158583299621750436769137314374860587496435967472
Line 1056, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_mp_regions/latest/run.log

  UVM_FATAL @ 4157478.3 ns: (flash_ctrl_mp_regions_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.flash_ctrl_mp_regions_vseq] wait timeout for alert_count == exp_alertcnt after do_mp_reg() alert_cnt:44  exp_alert_cnt:45
  UVM_INFO @ 4157478.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.flash_ctrl_mp_regions.33620071319455432539497350750129142986947902759944989419745303731370299397913
Line 649, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_mp_regions/latest/run.log

  UVM_FATAL @ 941815.9 ns: (flash_ctrl_mp_regions_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.flash_ctrl_mp_regions_vseq] wait timeout for alert_count == exp_alertcnt after do_mp_reg() alert_cnt:22  exp_alert_cnt:23
  UVM_INFO @ 941815.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 2 failures:
- Test flash_ctrl_rw_evict_all_en has 2 failures.
  - 16.flash_ctrl_rw_evict_all_en.61794504893007045080764767324010704280756486367648028112711015939099776043228
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 19309.0 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 19309.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 23.flash_ctrl_rw_evict_all_en.35530319071870318489046926971732552953123555006812437602599880559400240258575
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/23.flash_ctrl_rw_evict_all_en/latest/run.log
```
  UVM_ERROR @ 19890.0 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 19890.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:301) scoreboard [scoreboard] alert fatal_err did not trigger max_delay:* has 1 failures:
- Test flash_ctrl_phy_host_grant_err has 1 failures.
  - 4.flash_ctrl_phy_host_grant_err.79782671945105355763825921453879371473373147627230394546557211894191454651440
    Line 297, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_phy_host_grant_err/latest/run.log
```
  UVM_ERROR @ 24885.3 ns: (cip_base_scoreboard.sv:301) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_err did not trigger max_delay:2000
  UVM_INFO @ 24885.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```