FLASH_CTRL Simulation Results

Thursday April 18 2024 19:02:27 UTC

GitHub Revision: d3942ca074

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 25859338206198790995583629940734127463564215244480240139741775999763579929205

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.655m	124.754us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.710s	19.947us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.380s	216.407us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.370s	27.963us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.361m	9.568ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.105m	1.640ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	18.690s	204.766us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.370s	27.963us	20	20	100.00
		flash_ctrl_csr_aliasing	1.105m	1.640ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.420s	35.422us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.690s	57.386us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	27.090s	41.355us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.987m	256.014us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	33.391m	338.384ms	3	3	100.00
		flash_ctrl_hw_rma_reset	17.512m	760.499ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.680s	17.712us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	50.590m	274.726ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	10.208m	4.659ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	5.418m	4.155ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.212h	349.225ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.591m	1.415ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	35.130s	584.044us	40	40	100.00
		flash_ctrl_rw_evict_all_en	36.210s	369.602us	39	40	97.50
		flash_ctrl_re_evict	39.080s	128.567us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	11.448m	2.704ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	11.448m	2.704ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	15.975m	46.982ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	25.480s	898.862us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	22.443m	6.045ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	41.439m	5.169ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	17.859m	717.704us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	44.758m	1.002ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.880s	155.903us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.754m	18.780ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.650s	29.737us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.230s	15.783us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	30.294m	736.976us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.076m	11.011ms	50	50	100.00
		flash_ctrl_otp_reset	2.261m	586.993us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	33.391m	338.384ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	3.867m	9.591ms	40	40	100.00
		flash_ctrl_intr_wr	1.926m	24.465ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	4.842m	66.270ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	7.526m	304.089ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.759m	41.614ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.257m	6.319ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.100s	78.011us	5	5	100.00
		flash_ctrl_ro_derr	2.355m	690.858us	10	10	100.00
		flash_ctrl_rw_derr	10.438m	4.430ms	10	10	100.00
		flash_ctrl_derr_detect	1.817m	274.884us	5	5	100.00
		flash_ctrl_integrity	10.021m	12.282ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.760s	43.323us	5	5	100.00
		flash_ctrl_ro_serr	2.189m	2.644ms	10	10	100.00
		flash_ctrl_rw_serr	11.284m	4.233ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.361m	1.455ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.374m	771.841us	5	5	100.00
V2	scramble	flash_ctrl_wo	3.503m	5.683ms	20	20	100.00
		flash_ctrl_write_word_sweep	13.960s	25.271us	1	1	100.00
		flash_ctrl_read_word_sweep	13.260s	29.957us	1	1	100.00
		flash_ctrl_ro	2.035m	2.342ms	20	20	100.00
		flash_ctrl_rw	9.433m	9.932ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	36.890s	513.637us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	15.743m	141.263ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.356m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.110s	67.388us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.900s	106.745us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.360s	232.301us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.360s	232.301us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.380s	216.407us	5	5	100.00
		flash_ctrl_csr_rw	17.370s	27.963us	20	20	100.00
		flash_ctrl_csr_aliasing	1.105m	1.640ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	33.820s	607.475us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.380s	216.407us	5	5	100.00
		flash_ctrl_csr_rw	17.370s	27.963us	20	20	100.00
		flash_ctrl_csr_aliasing	1.105m	1.640ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	33.820s	607.475us	20	20	100.00
V2		TOTAL			1012	1013	99.90
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	15.690s	40.102us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	15.690s	40.102us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	15.690s	40.102us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	15.690s	40.102us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.150s	45.066us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.332h	3.955ms	5	5	100.00
		flash_ctrl_tl_intg_err	14.976m	881.524us	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	14.976m	881.524us	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	14.976m	881.524us	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.430s	824.912us	3	3	100.00
		flash_ctrl_wr_intg	14.380s	47.694us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.655m	124.754us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.261m	586.993us	80	80	100.00
		flash_ctrl_disable	22.650s	29.737us	50	50	100.00
		flash_ctrl_sec_info_access	1.545m	21.060ms	50	50	100.00
		flash_ctrl_connect	16.230s	15.783us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.330s	20.904us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.370s	27.963us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.690s	40.102us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.370s	27.963us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.690s	40.102us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.370s	27.963us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	15.690s	40.102us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.650s	29.737us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.430s	824.912us	3	3	100.00
		flash_ctrl_access_after_disable	13.600s	52.480us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.650s	29.737us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	25.480s	898.862us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	9.433m	9.932ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	11.284m	4.233ms	10	10	100.00
		flash_ctrl_rw_derr	10.438m	4.430ms	10	10	100.00
		flash_ctrl_integrity	10.021m	12.282ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	33.391m	338.384ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.332h	3.955ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.332h	3.955ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.332h	3.955ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.332h	3.955ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	1.333m	864.778us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.270s	23.817us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	13.990s	49.554us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.332h	3.955ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.332h	3.955ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.332h	3.955ms	5	5	100.00
V2S		TOTAL			144	144	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	44.290s	176.769us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1277	1278	99.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	54	98.18
V2S	12	12	12	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.41	95.84	94.01	98.85	91.84	98.22	98.01	98.09

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:
  • Test flash_ctrl_rw_evict_all_en has 1 failures.

    • 12.flash_ctrl_rw_evict_all_en.51775003708472686305251557945993422210644492712614716566783855614302151153897
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict_all_en/latest/run.log

        UVM_ERROR @ 23911.1 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 23911.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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