FLASH_CTRL Simulation Results

Sunday April 21 2024 19:02:51 UTC

GitHub Revision: 4fd94db59a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 89274329416853274976097168471417145417282051311181377329444669936981619711436

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.689m	182.614us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	27.120s	45.407us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	45.750s	90.266us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	18.120s	135.453us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.358m	4.458ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	52.900s	914.705us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.570s	423.966us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	18.120s	135.453us	20	20	100.00
		flash_ctrl_csr_aliasing	52.900s	914.705us	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.450s	45.199us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.450s	62.460us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.900s	21.908us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.035m	274.787us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	30.709m	105.965ms	3	3	100.00
		flash_ctrl_hw_rma_reset	16.177m	80.145ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.850s	47.705us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	45.827m	259.540ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	6.740m	2.129ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	1.060m	3.940ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.160h	48.914ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.198m	5.559ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	36.230s	401.773us	39	40	97.50
		flash_ctrl_rw_evict_all_en	37.260s	653.029us	40	40	100.00
		flash_ctrl_re_evict	40.160s	487.139us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	11.400m	2.970ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	11.400m	2.970ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	13.704m	170.984ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	28.650s	518.310us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	22.582m	1.798ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	43.763m	6.907ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	16.569m	11.832ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	48.802m	6.468ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.840s	16.291us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	2.981m	1.677ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	23.390s	12.479us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.520s	14.761us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	23.756m	984.337us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	3.999m	5.145ms	50	50	100.00
		flash_ctrl_otp_reset	2.263m	69.375us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	30.709m	105.965ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	3.830m	12.010ms	40	40	100.00
		flash_ctrl_intr_wr	1.722m	5.025ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	5.285m	35.584ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	7.951m	191.293ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.481m	3.931ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.288m	6.358ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.450s	19.187us	5	5	100.00
		flash_ctrl_ro_derr	2.586m	1.013ms	10	10	100.00
		flash_ctrl_rw_derr	9.647m	6.107ms	10	10	100.00
		flash_ctrl_derr_detect	1.749m	152.438us	5	5	100.00
		flash_ctrl_integrity	12.610m	18.252ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.430s	24.196us	5	5	100.00
		flash_ctrl_ro_serr	2.431m	1.507ms	10	10	100.00
		flash_ctrl_rw_serr	9.607m	30.530ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.372m	1.540ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.307m	762.544us	5	5	100.00
V2	scramble	flash_ctrl_wo	3.417m	5.342ms	20	20	100.00
		flash_ctrl_write_word_sweep	16.430s	157.067us	1	1	100.00
		flash_ctrl_read_word_sweep	14.460s	302.509us	1	1	100.00
		flash_ctrl_ro	1.947m	1.800ms	20	20	100.00
		flash_ctrl_rw	10.502m	10.624ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	36.090s	1.191ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	16.426m	157.501ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.086m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.740s	49.260us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.030s	17.303us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	19.390s	120.001us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	19.390s	120.001us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	45.750s	90.266us	5	5	100.00
		flash_ctrl_csr_rw	18.120s	135.453us	20	20	100.00
		flash_ctrl_csr_aliasing	52.900s	914.705us	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.150s	356.443us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	45.750s	90.266us	5	5	100.00
		flash_ctrl_csr_rw	18.120s	135.453us	20	20	100.00
		flash_ctrl_csr_aliasing	52.900s	914.705us	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.150s	356.443us	20	20	100.00
V2		TOTAL			1012	1013	99.90
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.350s	29.640us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.350s	29.640us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.350s	29.640us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.350s	29.640us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	15.970s	14.665us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.384h	2.721ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.063m	806.993us	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.063m	806.993us	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.063m	806.993us	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.090s	65.716us	3	3	100.00
		flash_ctrl_wr_intg	14.730s	237.069us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.689m	182.614us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.263m	69.375us	80	80	100.00
		flash_ctrl_disable	23.390s	12.479us	50	50	100.00
		flash_ctrl_sec_info_access	1.594m	29.998ms	50	50	100.00
		flash_ctrl_connect	16.520s	14.761us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.170s	77.723us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	18.120s	135.453us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.350s	29.640us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	18.120s	135.453us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.350s	29.640us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	18.120s	135.453us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.350s	29.640us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	23.390s	12.479us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.090s	65.716us	3	3	100.00
		flash_ctrl_access_after_disable	13.830s	40.561us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	23.390s	12.479us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	28.650s	518.310us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	10.502m	10.624ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	9.607m	30.530ms	10	10	100.00
		flash_ctrl_rw_derr	9.647m	6.107ms	10	10	100.00
		flash_ctrl_integrity	12.610m	18.252ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	30.709m	105.965ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.384h	2.721ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.384h	2.721ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.384h	2.721ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.384h	2.721ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	21.490s	915.769us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.340s	43.067us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.320s	16.879us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.384h	2.721ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.384h	2.721ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.384h	2.721ms	5	5	100.00
V2S		TOTAL			144	144	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	42.630s	145.268us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1277	1278	99.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	54	98.18
V2S	12	12	12	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.56	95.85	94.26	98.85	92.52	98.27	98.11	98.09

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * has 1 failures:
  • Test flash_ctrl_rw_evict has 1 failures.

    • 19.flash_ctrl_rw_evict.30229541264101470441885339369432117138405320383675110550537608939635919700376
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_rw_evict/latest/run.log

        UVM_ERROR @ 80425.3 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0
        UVM_INFO @ 80425.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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