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ASSERTPROPERTIESSEQUENCES
Total992010
Category 0992010

Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total992010
Severity 0992010

Summary for Assertions
NUMBERPERCENT
Total Number992100.00
Uncovered171.71
Success97598.29
Failure00.00
Incomplete151.51
Without Attempts00.00

Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered330.00
All Matches770.00
First Matches770.00
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ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETE
tb.dut.tlul_assert_device.gen_assert_final[22].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[230].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[231].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[232].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[233].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[234].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[235].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[236].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[237].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[238].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[239].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[23].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[240].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[241].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[242].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[243].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[244].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[245].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[246].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[247].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[248].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[249].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[24].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[250].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[251].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[252].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[253].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[254].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[255].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[25].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[26].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[27].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[28].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[29].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[2].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[30].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[31].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[32].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[33].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[34].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[35].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[36].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[37].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[38].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[39].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[3].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[41].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[42].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A 001272127200
tb.dut.tlul_assert_device.gen_device.aDataKnown_M 00428226574492306900
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A 00428225880600100
tb.dut.tlul_assert_device.gen_device.contigMask_M 004282265743357924500
tb.dut.tlul_assert_device.gen_device.dDataKnown_A 004279999243902536700
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A 00428225880423800
tb.dut.tlul_assert_device.gen_device.legalAParam_M 004282265743626857400
tb.dut.tlul_assert_device.gen_device.legalDParam_A 004282265744691240300
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M 004282265743626857400
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A 004282265744691240300
tb.dut.tlul_assert_device.gen_device.respOpcode_A 004282265744691240300
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A 004282265744691240300
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A 00428225880485400
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A 00428225880554100
tb.dut.tlul_assert_device.p_dbw.TlDbw_A 001277127700
tb.dut.u_ctrl_arb.u_state_regs.AssertConnected_A 001062106200
tb.dut.u_ctrl_arb.u_state_regs_A 0042507685942419504100
tb.dut.u_disable_buf.NumCopiesMustBeGreaterZero_A 001062106200
tb.dut.u_disable_buf.OutputsKnown_A 0042507678342419496500
tb.dut.u_disable_buf.gen_no_flops.OutputDelay_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[0].u_core.ArbCntMax_A 00425076783229017400
tb.dut.u_eflash.gen_flash_cores[0].u_core.CtrlPrio_A 00425076783229017400
tb.dut.u_eflash.gen_flash_cores[0].u_core.HostTransIdleChk_A 004250767832351213500
tb.dut.u_eflash.gen_flash_cores[0].u_core.NoRemainder_A 001062106200
tb.dut.u_eflash.gen_flash_cores[0].u_core.OneHotReqs_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[0].u_core.Pow2Multiple_A 001062106200
tb.dut.u_eflash.gen_flash_cores[0].u_core.RdTxnCheck_A 0042485013342396831500
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.OneDonePerTxn_A 00425076783121646400
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.PostPackRule_A 004250767831712700
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.PrePackRule_A 00425076783835500
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.WidthCheck_A 001062106200
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_state_regs.AssertConnected_A 001062106200
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_state_regs_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.NumCopiesMustBeGreaterZero_A 001062106200
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.OutputsKnown_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_disable_buf.gen_no_flops.OutputDelay_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckHotOne_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A 001062106200
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesReady_A 0042507678312225120500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesValid_A 0042507678312225120500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GrantKnown_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IdxKnown_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IndexIsCorrect_A 0042507678312225120500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A 004250767834667705700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.Priority_A 0042507678312846777500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A 0042507678312225120500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A 0042507678312225120500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqImpliesValid_A 0042507678312846777500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ValidKnown_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckHotOne_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A 001062106200
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesReady_A 0042507678312225118900
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesValid_A 0042507678312225118900
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GrantKnown_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IdxKnown_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IndexIsCorrect_A 0042507678312225118900
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A 004250767834667699400
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.Priority_A 0042507678312846782200
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A 0042507678312225118900
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A 0042507678312225118900
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqImpliesValid_A 0042507678312846782200
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ValidKnown_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.BufferMatchEcc_A 0042507678383871700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.ExclusiveOps_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.ExclusiveProgHazard_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.ExclusiveState_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.ForwardCheck_A 00425076783203254300
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.IdleCheck_A 004250767835374050100
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.MaxBufs_A 001062106200
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.OneHotAlloc_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.OneHotMatch_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.OneHotRspMatch_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.OneHotUpdate_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf.AllocCheck_A 0042507678372656400
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[0].u_rd_buf.UpdateCheck_A 0042507678372656300
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf.AllocCheck_A 0042507678372621700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[1].u_rd_buf.UpdateCheck_A 0042507678372621500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf.AllocCheck_A 0042507678372614000
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[2].u_rd_buf.UpdateCheck_A 0042507678372613800
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf.AllocCheck_A 0042507678372557500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.gen_bufs[3].u_rd_buf.UpdateCheck_A 0042507678372557400
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.DataKnown_A 004250767831300784900
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.DepthKnown_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.RvalidKnown_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.WreadyKnown_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.gen_normal_fifo.depthShallNotExceedParamDepth 004250767831300784900
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.BufferDecrUnderRun_A 00425076783374320700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.BufferDepRsp_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.BufferIncrOverFlow_A 00425076783374321400
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.DepBufferRspOrder_A 00425076783880653700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.DataKnown_A 004248501331402369800
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.DepthKnown_A 0042485013342396831500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.RvalidKnown_A 0042485013342396831500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.WreadyKnown_A 0042485013342396831500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.depthShallNotExceedParamDepth 004248501331402369800
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.DataKnown_A 004248501335373213800
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.DepthKnown_A 0042485013342396831500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.RvalidKnown_A 0042485013342396831500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.WreadyKnown_A 0042485013342396831500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 004248501335373213800
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.CheckHotOne_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.CheckNGreaterZero_A 001062106200
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.GntImpliesReady_A 00425076783286128100
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.GntImpliesValid_A 00425076783286128100
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.GrantKnown_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.IdxKnown_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.IndexIsCorrect_A 00425076783286128100
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.NoReadyValidNoGrant_A 0042507678332018889700
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReadyAndValidImplyGrant_A 00425076783286128100
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqAndReadyImplyGrant_A 00425076783286128100
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqImpliesValid_A 004250767839885094100
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.RoundRobin_A 004250767833185301056
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ValidKnown_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_state_regs.AssertConnected_A 001062106200
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_state_regs_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.DataKnown_A 00424850133294190400
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.DepthKnown_A 0042485013342396831500
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.RvalidKnown_A 0042485013342396831500
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.WreadyKnown_A 0042485013342396831500
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 00424850133294190400
tb.dut.u_eflash.gen_flash_cores[1].u_core.ArbCntMax_A 00425076783204750100
tb.dut.u_eflash.gen_flash_cores[1].u_core.CtrlPrio_A 00425076783204750100
tb.dut.u_eflash.gen_flash_cores[1].u_core.HostTransIdleChk_A 004250767832308302800
tb.dut.u_eflash.gen_flash_cores[1].u_core.NoRemainder_A 001062106200
tb.dut.u_eflash.gen_flash_cores[1].u_core.OneHotReqs_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[1].u_core.Pow2Multiple_A 001062106200
tb.dut.u_eflash.gen_flash_cores[1].u_core.RdTxnCheck_A 0042485013342396831500
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.OneDonePerTxn_A 00425076783118566700
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.PostPackRule_A 004250767831257800
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.PrePackRule_A 00425076783649300
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.WidthCheck_A 001062106200
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_state_regs.AssertConnected_A 001062106200
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_state_regs_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.NumCopiesMustBeGreaterZero_A 001062106200
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.OutputsKnown_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_no_flops.OutputDelay_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckHotOne_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A 001062106200
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesReady_A 0042507678310908665300
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesValid_A 0042507678310908665300
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GrantKnown_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IdxKnown_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IndexIsCorrect_A 0042507678310908665300
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A 004250767834365803000
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.Priority_A 0042507678311488067400
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A 0042507678310908665300
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A 0042507678310908665300
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqImpliesValid_A 0042507678311488067400
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ValidKnown_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckHotOne_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A 001062106200
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesReady_A 0042507678310908657000
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesValid_A 0042507678310908657000
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GrantKnown_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IdxKnown_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IndexIsCorrect_A 0042507678310908657000
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A 004250767834365803000
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.Priority_A 0042507678311488059100
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A 0042507678310908657000
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A 0042507678310908657000
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqImpliesValid_A 0042507678311488059100
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ValidKnown_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.BufferMatchEcc_A 0042507678378646200
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ExclusiveOps_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ExclusiveProgHazard_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ExclusiveState_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ForwardCheck_A 00425076783193896000
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.IdleCheck_A 004250767835031064700
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.MaxBufs_A 001062106200
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotAlloc_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotMatch_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotRspMatch_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotUpdate_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf.AllocCheck_A 0042507678371075800
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf.UpdateCheck_A 0042507678371075700
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf.AllocCheck_A 0042507678371048100
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf.UpdateCheck_A 0042507678371048000
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf.AllocCheck_A 0042507678371029400
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf.UpdateCheck_A 0042507678371029000
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf.AllocCheck_A 0042507678370994500
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf.UpdateCheck_A 0042507678370994400
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.DataKnown_A 004250767831160518300
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.DepthKnown_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.RvalidKnown_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.WreadyKnown_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.gen_normal_fifo.depthShallNotExceedParamDepth 004250767831160518300
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep.BufferDecrUnderRun_A 00425076783362793300
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep.BufferDepRsp_A 0042507678342419496500
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep.BufferIncrOverFlow_A 00425076783362794200
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