FLASH_CTRL Simulation Results

Tuesday April 23 2024 19:02:21 UTC

GitHub Revision: 41bc3e0c7f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60193594966460162319774997373112005644450303415496697929754976735654535188776

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	4.545m	1.362ms	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.430s	18.363us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	47.680s	76.239us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.800s	225.669us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.302m	3.218ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.070m	1.273ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.440s	44.821us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.800s	225.669us	20	20	100.00
		flash_ctrl_csr_aliasing	1.070m	1.273ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.650s	20.427us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.970s	42.010us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.870s	51.672us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.108m	166.857us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	32.681m	169.955ms	3	3	100.00
		flash_ctrl_hw_rma_reset	15.959m	160.194ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.880s	24.956us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	46.008m	258.057ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	10.033m	4.008ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	41.440s	419.273us	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.239h	135.977ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.728m	14.049ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	36.080s	97.592us	39	40	97.50
		flash_ctrl_rw_evict_all_en	32.650s	93.526us	40	40	100.00
		flash_ctrl_re_evict	38.700s	241.211us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.550m	1.398ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.550m	1.398ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	21.313m	16.961ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	29.310s	1.586ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	15.442m	1.649ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	40.049m	10.132ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	17.828m	4.754ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	51.592m	1.410ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.650s	15.233us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.086m	4.551ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.410s	19.209us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.370s	25.333us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	26.286m	1.380ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.096m	3.018ms	50	50	100.00
		flash_ctrl_otp_reset	2.284m	154.634us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	32.681m	169.955ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	3.631m	4.584ms	40	40	100.00
		flash_ctrl_intr_wr	1.802m	4.826ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	5.090m	11.618ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	8.463m	167.400ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.583m	3.862ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.240m	3.576ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.540s	19.308us	5	5	100.00
		flash_ctrl_ro_derr	2.677m	9.890ms	10	10	100.00
		flash_ctrl_rw_derr	12.890m	7.983ms	10	10	100.00
		flash_ctrl_derr_detect	1.762m	390.623us	5	5	100.00
		flash_ctrl_integrity	10.356m	22.649ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.720s	187.400us	5	5	100.00
		flash_ctrl_ro_serr	2.593m	688.770us	10	10	100.00
		flash_ctrl_rw_serr	11.422m	4.144ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.334m	741.222us	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.049m	1.302ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.625m	5.125ms	20	20	100.00
		flash_ctrl_write_word_sweep	14.070s	103.771us	1	1	100.00
		flash_ctrl_read_word_sweep	14.040s	40.297us	1	1	100.00
		flash_ctrl_ro	2.029m	1.271ms	20	20	100.00
		flash_ctrl_rw	9.698m	3.684ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	37.370s	1.190ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	21.239m	86.815ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.483m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.290s	387.415us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.110s	22.127us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.490s	223.211us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.490s	223.211us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	47.680s	76.239us	5	5	100.00
		flash_ctrl_csr_rw	17.800s	225.669us	20	20	100.00
		flash_ctrl_csr_aliasing	1.070m	1.273ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.590s	165.231us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	47.680s	76.239us	5	5	100.00
		flash_ctrl_csr_rw	17.800s	225.669us	20	20	100.00
		flash_ctrl_csr_aliasing	1.070m	1.273ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.590s	165.231us	20	20	100.00
V2		TOTAL			1012	1013	99.90
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.120s	60.369us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.120s	60.369us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.120s	60.369us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.120s	60.369us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.110s	12.127us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.388h	5.718ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.241m	797.442us	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.241m	797.442us	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.241m	797.442us	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	31.920s	64.026us	3	3	100.00
		flash_ctrl_wr_intg	14.890s	83.742us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	4.545m	1.362ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.284m	154.634us	80	80	100.00
		flash_ctrl_disable	22.410s	19.209us	50	50	100.00
		flash_ctrl_sec_info_access	1.353m	4.208ms	50	50	100.00
		flash_ctrl_connect	16.370s	25.333us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	13.700s	44.328us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.800s	225.669us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.120s	60.369us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.800s	225.669us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.120s	60.369us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.800s	225.669us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.120s	60.369us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.410s	19.209us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	31.920s	64.026us	3	3	100.00
		flash_ctrl_access_after_disable	13.560s	22.450us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.410s	19.209us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	29.310s	1.586ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	9.698m	3.684ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	11.422m	4.144ms	10	10	100.00
		flash_ctrl_rw_derr	12.890m	7.983ms	10	10	100.00
		flash_ctrl_integrity	10.356m	22.649ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	32.681m	169.955ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.388h	5.718ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.388h	5.718ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.388h	5.718ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.388h	5.718ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	24.880s	655.909us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.360s	161.671us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.960s	26.180us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.388h	5.718ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.388h	5.718ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.388h	5.718ms	5	5	100.00
V2S		TOTAL			144	144	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	47.350s	92.098us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1277	1278	99.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	54	98.18
V2S	12	12	12	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.53	95.84	94.13	98.85	92.52	98.24	98.00	98.09

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:
  • Test flash_ctrl_rw_evict has 1 failures.

    • 15.flash_ctrl_rw_evict.60168880592520146818242622210986503507299404099364878912305019847364953062649
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_rw_evict/latest/run.log

        UVM_ERROR @ 22961.5 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 22961.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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