GPIO Simulation Results

Sunday May 21 2023 07:04:58 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 3002339765

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.490s	344.129us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.470s	79.110us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.680s	27.691us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.640s	49.761us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.320s	769.700us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.780s	25.334us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.340s	61.438us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.640s	49.761us	20	20	100.00
		gpio_csr_aliasing	0.780s	25.334us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.400s	113.677us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.290s	274.520us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.980s	42.495us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.480s	319.196us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.590s	341.633us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.720s	124.444us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.110s	949.848us	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.220s	2.008ms	50	50	100.00
V2	full_random	gpio_full_random	1.160s	759.715us	50	50	100.00
V2	stress_all	gpio_stress_all	3.633m	9.950ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.680s	13.179us	50	50	100.00
V2	intr_test	gpio_intr_test	0.640s	26.170us	30	50	60.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.340s	160.846us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.340s	160.846us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.640s	49.761us	20	20	100.00
		gpio_same_csr_outstanding	0.860s	115.936us	20	20	100.00
		gpio_csr_aliasing	0.780s	25.334us	5	5	100.00
		gpio_csr_hw_reset	0.680s	27.691us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.640s	49.761us	20	20	100.00
		gpio_same_csr_outstanding	0.860s	115.936us	20	20	100.00
		gpio_csr_aliasing	0.780s	25.334us	5	5	100.00
		gpio_csr_hw_reset	0.680s	27.691us	5	5	100.00
V2		TOTAL			620	640	96.88
V2S	tl_intg_err	gpio_tl_intg_err	1.450s	135.343us	20	20	100.00
		gpio_sec_cm	1.040s	414.396us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.450s	135.343us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	50.097m	728.762ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			850	870	97.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	14	14	13	92.86
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.61	99.07	99.10	100.00	--	99.80	99.68	100.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:455) [gpio_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRgpio_reg_block.intr_state

has 20 failures:

Test gpio_intr_test has 20 failures.

6.gpio_intr_test.1287106440
Line 220, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/6.gpio_intr_test/latest/run.log

  UVM_ERROR @   9246483 ps: (cip_base_vseq.sv:455) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 1367269063 [0x517edec7]) when reading the intr CSRgpio_reg_block.intr_state
  UVM_INFO @   9246483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.gpio_intr_test.201557927
Line 221, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/7.gpio_intr_test/latest/run.log

  UVM_ERROR @   3154562 ps: (cip_base_vseq.sv:455) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 2617081033 [0x9bfd7cc9]) when reading the intr CSRgpio_reg_block.intr_state
  UVM_INFO @   3154562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 18 more failures.