V1 |
smoke |
gpio_smoke |
1.420s |
168.557us |
50 |
50 |
100.00 |
|
|
gpio_smoke_no_pullup_pulldown |
1.460s |
950.533us |
50 |
50 |
100.00 |
|
|
gpio_smoke_en_cdc_prim |
1.560s |
146.182us |
50 |
50 |
100.00 |
|
|
gpio_smoke_no_pullup_pulldown_en_cdc_prim |
1.470s |
50.066us |
50 |
50 |
100.00 |
V1 |
csr_hw_reset |
gpio_csr_hw_reset |
0.670s |
55.163us |
5 |
5 |
100.00 |
V1 |
csr_rw |
gpio_csr_rw |
0.680s |
35.195us |
20 |
20 |
100.00 |
V1 |
csr_bit_bash |
gpio_csr_bit_bash |
3.330s |
1.258ms |
5 |
5 |
100.00 |
V1 |
csr_aliasing |
gpio_csr_aliasing |
0.830s |
127.357us |
5 |
5 |
100.00 |
V1 |
csr_mem_rw_with_rand_reset |
gpio_csr_mem_rw_with_rand_reset |
1.270s |
99.646us |
20 |
20 |
100.00 |
V1 |
regwen_csr_and_corresponding_lockable_csr |
gpio_csr_rw |
0.680s |
35.195us |
20 |
20 |
100.00 |
|
|
gpio_csr_aliasing |
0.830s |
127.357us |
5 |
5 |
100.00 |
V1 |
|
TOTAL |
|
|
255 |
255 |
100.00 |
V2 |
direct_and_masked_out |
gpio_random_dout_din |
1.280s |
59.138us |
50 |
50 |
100.00 |
|
|
gpio_random_dout_din_no_pullup_pulldown |
1.390s |
303.069us |
50 |
50 |
100.00 |
V2 |
out_in_regs_read_write |
gpio_dout_din_regs_random_rw |
0.930s |
198.984us |
50 |
50 |
100.00 |
V2 |
gpio_interrupt_programming |
gpio_intr_rand_pgm |
1.420s |
86.120us |
50 |
50 |
100.00 |
V2 |
random_interrupt_trigger |
gpio_rand_intr_trigger |
3.560s |
777.198us |
50 |
50 |
100.00 |
V2 |
interrupt_and_noise_filter |
gpio_intr_with_filter_rand_intr_event |
3.420s |
185.631us |
50 |
50 |
100.00 |
V2 |
noise_filter_stress |
gpio_filter_stress |
29.350s |
8.663ms |
50 |
50 |
100.00 |
V2 |
regs_long_reads_and_writes |
gpio_random_long_reg_writes_reg_reads |
6.040s |
1.627ms |
50 |
50 |
100.00 |
V2 |
full_random |
gpio_full_random |
1.050s |
186.251us |
50 |
50 |
100.00 |
V2 |
stress_all |
gpio_stress_all |
3.943m |
66.430ms |
50 |
50 |
100.00 |
V2 |
alert_test |
gpio_alert_test |
0.650s |
111.985us |
50 |
50 |
100.00 |
V2 |
intr_test |
gpio_intr_test |
0.740s |
19.296us |
50 |
50 |
100.00 |
V2 |
tl_d_oob_addr_access |
gpio_tl_errors |
2.650s |
963.074us |
20 |
20 |
100.00 |
V2 |
tl_d_illegal_access |
gpio_tl_errors |
2.650s |
963.074us |
20 |
20 |
100.00 |
V2 |
tl_d_outstanding_access |
gpio_csr_rw |
0.680s |
35.195us |
20 |
20 |
100.00 |
|
|
gpio_same_csr_outstanding |
0.890s |
68.067us |
20 |
20 |
100.00 |
|
|
gpio_csr_aliasing |
0.830s |
127.357us |
5 |
5 |
100.00 |
|
|
gpio_csr_hw_reset |
0.670s |
55.163us |
5 |
5 |
100.00 |
V2 |
tl_d_partial_access |
gpio_csr_rw |
0.680s |
35.195us |
20 |
20 |
100.00 |
|
|
gpio_same_csr_outstanding |
0.890s |
68.067us |
20 |
20 |
100.00 |
|
|
gpio_csr_aliasing |
0.830s |
127.357us |
5 |
5 |
100.00 |
|
|
gpio_csr_hw_reset |
0.670s |
55.163us |
5 |
5 |
100.00 |
V2 |
|
TOTAL |
|
|
640 |
640 |
100.00 |
V2S |
tl_intg_err |
gpio_tl_intg_err |
1.500s |
131.220us |
20 |
20 |
100.00 |
|
|
gpio_sec_cm |
0.920s |
358.036us |
5 |
5 |
100.00 |
V2S |
sec_cm_bus_integrity |
gpio_tl_intg_err |
1.500s |
131.220us |
20 |
20 |
100.00 |
V2S |
|
TOTAL |
|
|
25 |
25 |
100.00 |
V3 |
stress_all_with_rand_reset |
gpio_stress_all_with_rand_reset |
41.262m |
267.422ms |
50 |
50 |
100.00 |
V3 |
|
TOTAL |
|
|
50 |
50 |
100.00 |
|
|
TOTAL |
|
|
970 |
970 |
100.00 |