GPIO Simulation Results

Sunday February 18 2024 20:02:30 UTC

GitHub Revision: 8faf04697a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 18983509472502570446328716692660256492766541929441074968843370054317032656232

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.610s	82.636us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.690s	58.613us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.700s	133.294us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.500s	325.380us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.680s	31.966us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.640s	55.816us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.050s	265.088us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.860s	101.262us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	3.070s	1.056ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.640s	55.816us	20	20	100.00
		gpio_csr_aliasing	0.860s	101.262us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.370s	45.948us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.400s	483.784us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.030s	790.026us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.720s	89.882us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.660s	119.041us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.900s	93.515us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.870s	556.382us	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	7.110s	1.416ms	50	50	100.00
V2	full_random	gpio_full_random	1.160s	81.255us	50	50	100.00
V2	stress_all	gpio_stress_all	3.817m	31.440ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.640s	21.885us	50	50	100.00
V2	intr_test	gpio_intr_test	0.710s	11.033us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.060s	424.028us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.060s	424.028us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.640s	55.816us	20	20	100.00
		gpio_same_csr_outstanding	0.950s	36.137us	20	20	100.00
		gpio_csr_aliasing	0.860s	101.262us	5	5	100.00
		gpio_csr_hw_reset	0.680s	31.966us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.640s	55.816us	20	20	100.00
		gpio_same_csr_outstanding	0.950s	36.137us	20	20	100.00
		gpio_csr_aliasing	0.860s	101.262us	5	5	100.00
		gpio_csr_hw_reset	0.680s	31.966us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.450s	98.378us	20	20	100.00
		gpio_sec_cm	0.920s	236.128us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.450s	98.378us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	42.200m	651.335ms	28	50	56.00
V3		TOTAL			28	50	56.00
		TOTAL			948	970	97.73

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:714) [gpio_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 21 failures:
  • Test gpio_stress_all_with_rand_reset has 21 failures.

    • 1.gpio_stress_all_with_rand_reset.13958455208469763390342085638011680432752234777491539439901210391647878924810
      Line 6000, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 52088956365 ps: (cip_base_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 52088956365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.gpio_stress_all_with_rand_reset.71489353527703187812263050525047894974729464040593296242729944537143090211966
      Line 3475, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/3.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11160057759 ps: (cip_base_vseq.sv:714) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 11160057759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 19 more failures.

• UVM_ERROR (cip_base_vseq.sv:756) [gpio_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset. has 1 failures:
  • Test gpio_stress_all_with_rand_reset has 1 failures.

    • 0.gpio_stress_all_with_rand_reset.12423263053099692954278738006934273148267320682061282092831967243927438571618
      Line 6142, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 194991918896 ps: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
        UVM_INFO @ 194991918896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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