GPIO Simulation Results

Sunday January 21 2024 20:02:56 UTC

GitHub Revision: 796f9fb805

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 82526748448873323296379810788667205332667151893362240729689214265893867671108

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke gpio_smoke 1.520s 370.528us 50 50 100.00
gpio_smoke_no_pullup_pulldown 1.510s 76.797us 50 50 100.00
gpio_smoke_en_cdc_prim 1.590s 593.441us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.760s 55.492us 50 50 100.00
V1 csr_hw_reset gpio_csr_hw_reset 0.730s 19.220us 5 5 100.00
V1 csr_rw gpio_csr_rw 0.690s 111.700us 20 20 100.00
V1 csr_bit_bash gpio_csr_bit_bash 3.430s 991.791us 5 5 100.00
V1 csr_aliasing gpio_csr_aliasing 0.900s 37.082us 5 5 100.00
V1 csr_mem_rw_with_rand_reset gpio_csr_mem_rw_with_rand_reset 1.720s 34.847us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr gpio_csr_rw 0.690s 111.700us 20 20 100.00
gpio_csr_aliasing 0.900s 37.082us 5 5 100.00
V1 TOTAL 255 255 100.00
V2 direct_and_masked_out gpio_random_dout_din 1.440s 66.961us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 1.410s 83.010us 50 50 100.00
V2 out_in_regs_read_write gpio_dout_din_regs_random_rw 0.950s 47.967us 50 50 100.00
V2 gpio_interrupt_programming gpio_intr_rand_pgm 1.490s 391.601us 50 50 100.00
V2 random_interrupt_trigger gpio_rand_intr_trigger 3.560s 353.825us 50 50 100.00
V2 interrupt_and_noise_filter gpio_intr_with_filter_rand_intr_event 3.950s 94.690us 50 50 100.00
V2 noise_filter_stress gpio_filter_stress 29.030s 914.051us 50 50 100.00
V2 regs_long_reads_and_writes gpio_random_long_reg_writes_reg_reads 6.220s 508.762us 50 50 100.00
V2 full_random gpio_full_random 1.320s 88.799us 50 50 100.00
V2 stress_all gpio_stress_all 3.986m 20.961ms 50 50 100.00
V2 alert_test gpio_alert_test 0.650s 41.479us 50 50 100.00
V2 intr_test gpio_intr_test 0.660s 15.423us 50 50 100.00
V2 tl_d_oob_addr_access gpio_tl_errors 3.180s 2.113ms 20 20 100.00
V2 tl_d_illegal_access gpio_tl_errors 3.180s 2.113ms 20 20 100.00
V2 tl_d_outstanding_access gpio_csr_rw 0.690s 111.700us 20 20 100.00
gpio_same_csr_outstanding 0.900s 77.029us 20 20 100.00
gpio_csr_aliasing 0.900s 37.082us 5 5 100.00
gpio_csr_hw_reset 0.730s 19.220us 5 5 100.00
V2 tl_d_partial_access gpio_csr_rw 0.690s 111.700us 20 20 100.00
gpio_same_csr_outstanding 0.900s 77.029us 20 20 100.00
gpio_csr_aliasing 0.900s 37.082us 5 5 100.00
gpio_csr_hw_reset 0.730s 19.220us 5 5 100.00
V2 TOTAL 640 640 100.00
V2S tl_intg_err gpio_tl_intg_err 1.460s 112.645us 20 20 100.00
gpio_sec_cm 0.950s 1.575ms 5 5 100.00
V2S sec_cm_bus_integrity gpio_tl_intg_err 1.460s 112.645us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset gpio_stress_all_with_rand_reset 57.149m 217.669ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 970 970 100.00

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 14 14 14 100.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.63 99.06 99.24 100.00 -- 99.80 99.68 100.00

Past Results