GPIO Simulation Results

Wednesday January 24 2024 20:02:24 UTC

GitHub Revision: 17d5a97c3b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 111545506019531132515166311410934274348263845011639206515682989027305484635840

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke gpio_smoke 1.470s 170.391us 50 50 100.00
gpio_smoke_no_pullup_pulldown 1.440s 108.276us 50 50 100.00
gpio_smoke_en_cdc_prim 1.670s 74.047us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.590s 54.466us 50 50 100.00
V1 csr_hw_reset gpio_csr_hw_reset 0.720s 23.346us 5 5 100.00
V1 csr_rw gpio_csr_rw 0.650s 12.296us 20 20 100.00
V1 csr_bit_bash gpio_csr_bit_bash 3.390s 496.307us 5 5 100.00
V1 csr_aliasing gpio_csr_aliasing 0.780s 93.680us 5 5 100.00
V1 csr_mem_rw_with_rand_reset gpio_csr_mem_rw_with_rand_reset 1.520s 116.423us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr gpio_csr_rw 0.650s 12.296us 20 20 100.00
gpio_csr_aliasing 0.780s 93.680us 5 5 100.00
V1 TOTAL 255 255 100.00
V2 direct_and_masked_out gpio_random_dout_din 1.350s 137.318us 50 50 100.00
gpio_random_dout_din_no_pullup_pulldown 1.360s 291.370us 50 50 100.00
V2 out_in_regs_read_write gpio_dout_din_regs_random_rw 0.970s 38.575us 50 50 100.00
V2 gpio_interrupt_programming gpio_intr_rand_pgm 1.420s 89.511us 48 50 96.00
V2 random_interrupt_trigger gpio_rand_intr_trigger 3.620s 478.147us 50 50 100.00
V2 interrupt_and_noise_filter gpio_intr_with_filter_rand_intr_event 3.660s 357.282us 49 50 98.00
V2 noise_filter_stress gpio_filter_stress 27.790s 3.887ms 50 50 100.00
V2 regs_long_reads_and_writes gpio_random_long_reg_writes_reg_reads 6.400s 1.927ms 50 50 100.00
V2 full_random gpio_full_random 1.040s 622.597us 47 50 94.00
V2 stress_all gpio_stress_all 3.664m 89.083ms 49 50 98.00
V2 alert_test gpio_alert_test 0.640s 16.211us 50 50 100.00
V2 intr_test gpio_intr_test 0.690s 131.433us 50 50 100.00
V2 tl_d_oob_addr_access gpio_tl_errors 3.160s 725.912us 20 20 100.00
V2 tl_d_illegal_access gpio_tl_errors 3.160s 725.912us 20 20 100.00
V2 tl_d_outstanding_access gpio_csr_rw 0.650s 12.296us 20 20 100.00
gpio_same_csr_outstanding 0.930s 78.774us 20 20 100.00
gpio_csr_aliasing 0.780s 93.680us 5 5 100.00
gpio_csr_hw_reset 0.720s 23.346us 5 5 100.00
V2 tl_d_partial_access gpio_csr_rw 0.650s 12.296us 20 20 100.00
gpio_same_csr_outstanding 0.930s 78.774us 20 20 100.00
gpio_csr_aliasing 0.780s 93.680us 5 5 100.00
gpio_csr_hw_reset 0.720s 23.346us 5 5 100.00
V2 TOTAL 633 640 98.91
V2S tl_intg_err gpio_tl_intg_err 1.560s 562.022us 20 20 100.00
gpio_sec_cm 0.960s 392.957us 5 5 100.00
V2S sec_cm_bus_integrity gpio_tl_intg_err 1.560s 562.022us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset gpio_stress_all_with_rand_reset 38.144m 235.597ms 48 50 96.00
V3 TOTAL 48 50 96.00
TOTAL 961 970 99.07

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 14 14 10 71.43
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.63 99.06 99.24 100.00 -- 99.80 99.68 100.00

Failure Buckets

Past Results