GPIO Simulation Results

Wednesday February 07 2024 20:02:46 UTC

GitHub Revision: 5c87d18988

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 42540109002295994234923032062842839138270099951232798724643629525632267455156

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.940s	124.530us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.530s	68.167us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.510s	700.196us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.480s	150.411us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.690s	32.689us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.650s	13.343us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.460s	3.327ms	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.830s	120.292us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.100s	38.716us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.650s	13.343us	20	20	100.00
		gpio_csr_aliasing	0.830s	120.292us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.570s	35.508us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.410s	204.048us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.070s	183.271us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.700s	242.602us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	4.150s	508.703us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	4.220s	185.939us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	30.960s	3.388ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	8.720s	901.938us	50	50	100.00
V2	full_random	gpio_full_random	1.190s	304.600us	50	50	100.00
V2	stress_all	gpio_stress_all	4.423m	19.409ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.670s	99.616us	50	50	100.00
V2	intr_test	gpio_intr_test	0.680s	15.029us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	2.970s	145.567us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	2.970s	145.567us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.650s	13.343us	20	20	100.00
		gpio_same_csr_outstanding	0.970s	35.773us	20	20	100.00
		gpio_csr_aliasing	0.830s	120.292us	5	5	100.00
		gpio_csr_hw_reset	0.690s	32.689us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.650s	13.343us	20	20	100.00
		gpio_same_csr_outstanding	0.970s	35.773us	20	20	100.00
		gpio_csr_aliasing	0.830s	120.292us	5	5	100.00
		gpio_csr_hw_reset	0.690s	32.689us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.760s	1.579ms	20	20	100.00
		gpio_sec_cm	0.930s	59.884us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.760s	1.579ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	42.157m	775.840ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			970	970	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	100.00

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